BLUENRG-2 datasheet(107/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

DocID030675 Rev 2

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3.11

Flash controller

3.11.1

Flash controller introduction

The BlueNRG-2 integrates a Flash controller to interface the embedded Flash memory.

Main features are:



Sector erase and mass erase



256 Kbyte Flash memory: 128 pages of 8 rows with 64 words each



Flash programming



Mass read



Enable readout protection



32-bit read access



32-bit write access in single write and 4x32-bit in burst write (reduce programming

time by 2)

3.11.2

Flash controller functional description

The BlueNRG-2 embeds up to 256 KB (65536 x 32-bit) of internal Flash memory. A Flash

interface implements instruction access and data access based on the AHB protocol. It

implements the logic necessary to carry out the Flash memory operations (Program/Erase)

controlled through the Flash registers.

Writing to Flash only allows clearing bits

from ‘1’ to ‘0’. This means any write from ‘0’ to ‘1’

implies erasing before performing a write.

Flash memory is composed of 128 pages containing 8 rows of 64 words (128 x 8 x 64 =

65536 words). Each word is 32-bit = 4 bytes long which means 256 KB of Flash.

The address inside the ADDRESS register is built as follows:

ADDRESS[13:0] = XADR[9:0] & YADR[5:0] with:



XADR[9:3] = page address



XADR[2:0] = row address



YADR[5:0] = word address (one word = four bytes)

One specific address can be written only twice between two erase actions even if

each writing only clears bits.

The Flash data retention is greater than 10 years at 85 °C. The Flash is rated to

have a Flash cycling of 10.000 write/erase cycles.

3.11.2.1

Reading Flash memory

There are two possible read accesses:



Read one single word: simple read as if RAM memory: read the desired Flash address

and get read data on the bus.



MASSREAD command: read the full Flash memory and compare with expected

content

There are two ways of using MASSREAD:

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