BLUENRG-2 datasheet(24/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

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combination of these signals is used to generate the input to the Cortex-M0 which is used

to reset the debug access port (DAP) of the processor. It is also used to generate the

signal which resets the debug logic of the Cortex-M0. The POR signal also resets the TAP

controller of the BlueNRG-2 and a part of the Flash controller (managing the Flash memory

boot, which does not need to be impacted by system resets).

The BOR is disabled by default, see the BlueNRG-1, BlueNRG-2 Programming manual

(PM0257) to enable it.

3.5.1.2

Power-on-sequence

The starting sequence of the BlueNRG-2 supply and reset signal is shown below.

Figure 8: BlueNRG-2 power-up sequence



The VBATx power must only be raised when RESETN pin is driven low.



The different VBATx (x=1..3) power can be raised separately or together.



The internal POR is released once internal LDOs are established and RCO clock is

ready.



The system starts on RCO 16 MHz clock system. The software is responsible for

configuring the XO 16/32 MHz when necessary.

The POR circuit is powered by a 1.2 V regulator, which must also be powered up with the

correct startup sequence. Before VBAT has reached the nominal value, RESETN line must

be kept low. An external RC circuit on RESETN pin will add a delay that can prevent

RESETN signal from going high before VBAT has reached the nominal value.

VBATx

x=1..3

RESETN

182 ms max

Internal POR

System clock

CPU under reset

CPU activity

CPU runing on

RCO 16M

CPU can switch on XO 16/32M

by SW

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