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BLUENRG-2 bảng dữ liệu(PDF) 32 Page - STMicroelectronics

tên linh kiện BLUENRG-2
Giải thích chi tiết về linh kiện  Bluetooth® low energy wireless system-on-chip
PDF  190 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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BLUENRG-2 bảng dữ liệu(HTML) 32 Page - STMicroelectronics

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Functional details
BlueNRG-2
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DocID030675 Rev 2
Several channels are available for conversion, the CHSEL selects the channel according to
Table 27: "ADC channels".
Table 27: ADC channels
CHSEL
Channels description
0
All switch open. No input
1
Single ended through ADC2 pin. InP = Vbias (internal), InN = ADC2 pin
2
Single ended through ADC1 pin. InP = ADC1 pin, InN = Vbias (internal)
3
Differential ADC1 pin
– ADC2 pin. InP = ADC1 pin, InN = ADC2 pin
4
Temperature sensor. InN=TEMP, InP = 0.6 V (internal)
5
Battery level detector. InN = BLD, InP = 0.6 V (internal)
6
Short. InP = InN = 0.6 V (internal)
The conversion can be single (CONT = 0) or continuous (CONT = 1). In continuous mode,
the conversion runs with a preprogrammed sampling rate, while in single step mode the
ADC performs a conversion and then stops.
The output data rate depends on the setting of OSR according to the following table.
Table 28: ADC data rate
OSR
Output data rate [Ksample/s]
0 (200)
5
1 (100)
10
2 (64)
15.625
3 (32)
31.25
The setting of the oversampling ratio (OSR) must be done according to the frequency of
the input signal (AC), while for DC signals, the best performance is with OSR = 200. In
order to achieve the best performance within the selected input voltage range, the
associated Vbias and attenuation value must be set through the corresponding registers
PGASEL and REFSEL values, as per the following table.
Table 29: ADC parameters settings
Vin range [V]
Vbias [V]
Attenuation [dB]
REFSEL value
PGASEL value
[0, 1.2]
0.6
0
2
0
[0, 2.4]
0.6
6.02
2
1
[0, 3.6]
0.6
9.54
2
2
[0.6, 1.8]
1.2
0
3
0
[1.2, 3.6]
1.2
6.02
3
1
The system can work in conjunction with an external MEMS microphone by setting
MIC_SEL. In this mode, an IO configured as PDM_CLK provides the clock to the external
microphone, while an IO configured as PDM_DATA received the PDM stream from the
external microphone. The external clock is 1.6 MHz (DIG_FILT_CLK = 0) or 0.8 MHz
(DIG_FILT_CLK = 1).
The output data rate changes with the OSR according to Table 30: "Output data rate with
microphone".



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