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BLUENRG-2 bảng dữ liệu(PDF) 62 Page - STMicroelectronics |
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BLUENRG-2 bảng dữ liệu(HTML) 62 Page - STMicroelectronics |
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62 / 190 page ![]() Functional details BlueNRG-2 62/190 DocID030675 Rev 2 Address offset Name RW Reset Description 0x0C SR R 0x00000003 Status Register. Refer to the detailed description below. 0x10 CPSR RW 0x00000000 Clock prescale register. Refer to the detailed description below. 0x14 IMSC RW 0x00000000 Interrupt mask set or clear register. Refer to the detailed description below. 0x18 RIS R 0x00000000 Raw interrupt status register. Refer to the detailed description below. 0x1C MIS R 0x00000000 Masked Interrupt Status Register. Refer to the detailed description below. 0x20 ICR W 0x00000000 Interrupt clear register. Refer to the detailed description below. 0x24 DMACR RW 0x00000000 SPI DMA control register. Refer to the detailed description below. 0x28 RXFRM RW 0x00000000 SPI Receive Frame register. Indicates the number of frames to receive from the slave. 0x2C CHN RW 0x00000000 Dummy character register 0x30 WDTXF RW 0x00000000 SPI transmit FIFO receive frame number. Indicates the number of frames to receive from the transmit FIFO 0x80 ITCR RW 0x00000000 Integration test control register. Refer to the detailed description below. 0x8C TDR RW 0x00000000 Test data register Table 56: SPI - CR0 register description: address offset SPI_BASE_ADDR+0x00 Bit Field name Reset RW Description 4:0 DSS 0x0 RW Data size select. (DSS+1) defines the number of bits: 0x00: Reserved. 0x01: Reserved. 0x02: Reserved. 0x03: 4-bit data. 0x04: 5-bit data. ... 0x1F: 32-bit data. 5 RESERVED 0x0 R RESERVED |
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