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BLUENRG-2 bảng dữ liệu(PDF) 26 Page - STMicroelectronics

tên linh kiện BLUENRG-2
Giải thích chi tiết về linh kiện  Bluetooth® low energy wireless system-on-chip
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BLUENRG-2 bảng dữ liệu(HTML) 26 Page - STMicroelectronics

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Functional details
BlueNRG-2
26/190
DocID030675 Rev 2
1.
If the register CKGEN_SOC->REASON_RST = 0, according to the CKGEN_BLE-
>REASON_RST the possible reasons are:
a.
Wakeup from IO9, IO10, IO11, IO12, IO13.
b.
Wakeup from internal timer: BLE timer 1 or BLE timer 2.
c.
POR or BOR
2.
If the register CKGEN_SOC->REASON_RST is not 0, according to its value the
possible reasons are:
a.
System reset
b.
Watchdog reset
c.
Lockup reset.
3.5.3
Switching to external clock
When the system is in preactive state (run from internal RO 16 MHz), the software
sequence to switch to active should include switch to external XO.
When the system uses an external XO at 32 MHz instead of 16 MHz, the following steps
need to be performed:
1.
Set the bitfield MHZ32_SEL of register SYSTEM_CTRL for the digital part.
2.
In the preactive state, inform the analog part of the external XO 32 MHz and send the
request to switch to ACTIVE2 state:
uint8_t config[] = { 0x02, 0x3A, 0x44, 0x02, 0x34, 0x1B, 0x00};
BLUE_CTRL->RADIO_CONFIG = 0x10000 | (uint16_t) ( (uint32_t)config &
0x0000FFFF );
while((BLUE_CTRL->RADIO_CONFIG & 0x10000) != 0);
3.
Wait until the state machine is in the active state by using the following routine:
while(CKGEN_BLE->CLK32K_IT == 0);
CKGEN_BLE->CLK32K_IT = 1;
CKGEN_BLE->CLK32K_COUNT = 23;
CKGEN_BLE->CLK32K_PERIOD = 0;
4.
Only after switching to the active state, write 0x15 in the COMMAND register of the
AHBUPCONV peripheral.
Around 10 system clock cycles after this last write, the system will run at 32 MHz except for
specific blocks requiring a fixed 16 MHz.
The application can make the bus and the core run at 16 MHz by writing 0x14 in
the COMMAND register of AHBUPCONV peripheral.
3.5.4
Clock and reset registers
CKGEN_SOC peripheral base address (CKGEN_SOC_BASE_ADDR) 0x40900000.
Table 14: CKGEN_SOC registers
Address offset
Name
RW
Reset
Description
0x00
CONTROL
RW
0x01FA03F0
Control clock and Reset of SOC. Refer to
the detailed description below.
0x08
REASON_RST
R
0x00000000
Indicates the Reset reason from Cortex-
M0. Refer to the detailed description
below.
0x1C
DIE_ID
R
0x00000100
Identification information of the device.
Refer to the detailed description below.



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