BLUENRG-2 datasheet(58/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

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DocID030675 Rev 2

3.8.2.3

SPI bit rate generation

The SPI bitrate is derived by dividing down the peripheral clock (CLK) by an even prescaler

value CPSDVSR from 2 to 254, the clock is further divided by a value from 1 to 256, which

is 1+SCR. The SPI frequency clock duty cycle is always 0.5.

3.8.2.4

SPI data endianness

All transfers can be sent and received with configurable endianness according the setting

of the (T/R)ENDN bit in the CR1 registers

The cases "00b" and "11b" of TENDN and RENDN are implemented for data frame size

from 4- to 32-bit. The cases "01b" and "10b" of TENDN and RENDN are implemented only

for the following data frame sizes: 16-bit, 24-bit and 32-bit. Transmit data endianness:

TENDN in CR1:

Table 53: SPI_OUT endianness

TENDN

Endianness

00b

The element is transmitted MSByte-first and MSbit-first.

01b

The element is transmitted LSByte-first and MSbit-first.

10b

The element is transmitted MSByte-first and LSbit-first.

11b

The element is transmitted LSByte-first and LSbit-first.

Table 54: SPI_IN endianness

RENDN

Endianness

00b

The element is received MSByte-first and MSbit-first.

01b

The element is received LSByte-first and MSbit-first.

10b

The element is received MSByte-first and LSbit-first.

11b

The element is received LSByte-first and LSbit-first.

3.8.2.5

SPI interrupts

There are six individual maskable interrupt sources generated by the SPI (single interrupt

signal that drives the NVIC):



Receive interrupt



Transmit interrupt



Timeout interrupt



Receive overrun interrupt



Transmit underrun interrupt



Transmit empty interrupt

The user can enable or disable the individual interrupt sources by changing the mask bits

in the IMSC register. Setting the appropriate mask bit to 1b enables the interrupt. The

status of the individual interrupt sources can be read from the RIS register (raw interrupt

status) or from the MIS register (masked interrupt status).

3.8.2.6

Receive interrupt

The receive interrupt is asserted when the number of data in receive FIFO reaches the

programmed trigger watermark level. The receive interrupt is cleared by reading data from

the receive FIFO until there are less data than the programmed watermark level.

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