BLUENRG-2 datasheet(61/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

DocID030675 Rev 2

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Switching between these different modes when SPI is enabled is possible. If the

transmission mode is deselected for another mode during a frame transmission, the new

mode will become active at the start of the next word.

3.8.2.13

SPI Master communication mode for National Semiconductor Microwire

standard

The FRF register field selects the SPI mode interface: the default value 0 indicates the

Motorola standard interface, while FRF = 2 selects the Microwire standard interface for the

3-wire SPI mode.

The hardware connection considers the SPI_IN and SPI_OUT pins connected together as

shown in the figure below. The two pins are handled internally to send and receive data.

Figure 12: MicroWire master and slave communication

The CSS register field specifies the length of the data to send and the DSS register field

specifies the length of the data to receive.

In reception mode, the quantity of data to read is specified in the DSS register field. The set

of the SSE register field, enables SPI for the communication. The user should wait for data

reception to end before attempting any reads. The SSE register field must be reset at the

end of the communication.

In transmission mode, the send data are written inside the TX FIFO and the quantity of

data to send is specified in the CSS register field. The SSE register field setting enables

SPI for the communication. When the busy flag is RESET, SPI communication is

terminated. The SSE register field must be reset at the end of the communication.

3.8.3

SPI registers

SPI peripheral base address (SPI_BASE_ADDR) 0x40400000.

Table 55: SPI registers

Address

offset

Name

Reset

Description

0x00

CR0

0x1C000000

Control Register 0. Refer to the detailed description

below.

0x04

CR1

0x00000000

Control Register 1. Refer to the detailed description

below.

0x08

0x00000000

Data Register. Refer to the detailed description

below.

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