BLUENRG-2 datasheet(103/190 Pages) STMICROELECTRONICS

103 / 190 page

BlueNRG-2

Functional details

DocID030675 Rev 2

103/190

Bit

Field name

Reset

Description

STD

0x0

Slave transaction done. STD is set when a slave operation

(write-to-slave or read-from-slave) has been executed. The

application shall read the related transaction status (SR

slave operation) and clear this interrupt (transaction

acknowledgment). A subsequent slave operation will be

notified (RISR:WTSR and RISR:RFSR interrupt bits assertion)

after clearing this interrupt, meanwhile the I2C clock line will

be stretched low. A subsequent master operation can be

issued (by writing the MCR register) after clearing this

interrupt. This interrupt is cleared by setting the related bit of

the ICR register:

0: Slave transaction acknowledged.

1: Slave transaction done (ready for acknowledgment).

23:21

RESERVED

0x0

RESERVED

MAL

0x0

Master arbitration lost. MAL is set when the master loses the

arbitration. The status code word in the SR contains a specific

error tag (CAUSE field) for this error condition. A collision

occurs when 2 stations transmit simultaneously 2 opposite

values on the serial line. The station that is pulling up the line,

identifies the collision reading a 0 value on the sda_in signal,

stops the transmission, leaves the bus and waits for the idle

state (STOP condition received) on the bus line before retrying

the same transaction. The station which transmits the first

unique zero wins the bus arbitration. This interrupt is cleared

by setting the related bit of the ICR register.

0: No master arbitration lost.

1: Master arbitration lost.

BERR

0x0

Bus Error. BERR is set when an unexpected Start/Stop

condition occurs during a transaction. The related actions are

different, depending on the type of operation in progress.The

status code word in the SR contains a specific error tag

(CAUSE field) for this error condition. This interrupt is cleared

by setting the related bit of the ICR register.

0: No bus error detection.

1: Bus error detection.

27:26

RESERVED

0x0

RESERVED

MTDWS

0x0

Master transaction done without stop. MTDWS is set when a

master operation (write or read) has been executed and a stop

(MCR:P field) is not programmed. The application shall read

the related transaction status (SR register), the pending data

in the RX FIFO (only for a master read operation) and clear

this interrupt (transaction acknowledgment). A subsequent

master operation can be issued (by writing the MCR register)

after clearing this interrupt. A subsequent slave operation will

be notified (RISR:WTSR and RISR:RFSR interrupt bits

assertion) after clearing this interrupt, meanwhile the I²C clock

line will be stretched low. This interrupt is cleared by setting

the related bit of the ICR register:

0: Master transaction acknowledged.

1: Master transaction done (ready for acknowledgment) and

stop is not applied into the I²C bus.

31:29

RESERVED

0x0

RESERVED

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