DS31256 datasheet(142/183 Pages) MAXIM

142 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

142 of 183

PVID1

PCI Vendor ID/Device ID Register 1

0x100h

LSB

Vendor ID (Read Only/Set to EAh)

Vendor ID (Read Only/Set to 13h)

Device ID (Read Only/Set to 34h)

MSB

Device ID (Read Only/Set to 31h)

Bits 0 to 15/Vendor ID. These read-only bits identify Dallas Semiconductor as the device’s manufacturer. The

vendor ID was assigned by the PCI Special Interest Group and is fixed at 13EAh.

Bits 16 to 31/Device ID. These read-only bits identify the DS31256 as the device being used. The device ID was

assigned by Dallas Semiconductor and is fixed at 3134h.

PCMD1

PCI Command/Status Register 1

0x104h

LSB

STEPC

PARC

VGA

MWEN

SCC

MASC

MSC

IOC

Reserved (Read Only/Set to All Zeros)

FBBEN

PSEC

FBBCT

UDF

66MHz

Reserved (Read Only/Set to All Zeros)

MSB

PPE

PSE

MABT

TABTM

TABT

DTS1

DTS0

PARR

Note: Read-only bits in the PCMD1 register are underlined; all other bits are read-write.

The lower word (bits 0 to 15) of the PCMD1 register is the command portion and is used for the PCI bus control.

When all bits in the lower word are set to 0, the device is logically disconnected from the bus for all accesses,

except for accesses to the configuration registers. The upper word (bits 16 to 31) is the status portion and is used

for status information. Reads to the status portion behave normally but writes are unique in that bits can be reset

(i.e., forced to 0) but not set (i.e., forced to 1). A bit in the status portion is reset when a 1 is written to that bit

position. Bit positions that have 0 written to them do not reset.

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