DS31256 datasheet(24/183 Pages) MAXIM

24 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

24 of 183

Signal Name:

PSTOP

Signal Description:

PCI Stop

Signal Type:

Input/Output (tri-state capable)

The target creates this active-low signal to signal the initiator to stop the current bus transaction. When the device

is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this

signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction,

PSTOP is tri-stated.

Signal Name:

PIDSEL

Signal Description:

PCI Initialization Device Select

Signal Type:

Input

This input signal is used as a chip select during configuration read and write transactions. This signal is disabled

when the local bus is set in configuration mode (LMS = 1). When PIDSEL is set high during the address phase

of a bus transaction and the bus command signals (PCBE0 to PCBE3) indicate a register read or write, the device

allows access to the PCI configuration registers, and the

PDEVSEL signal is asserted during the PCLK cycle.

PIDSEL is sampled on the rising edge of PCLK.

Signal Name:

PDEVSEL

Signal Description:

PCI Device Select

Signal Type:

Input/Output (tri-state capable)

The target creates this active-low signal when it has decoded the address sent to it by the initiator as its own to

indicate that the address is valid. If the device is an initiator and does not see this signal asserted within six PCLK

cycles, the bus transaction is aborted and the PCI host is alerted. When the device is a target, this signal is an

output and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is

sampled on the rising edge of PCLK. When the device is not involved in a bus transaction,

PDEVSEL is tri-stated.

Signal Name:

PREQ

Signal Description:

PCI Bus Request

Signal Type:

Output (tri-state capable)

The initiator asserts this active-low signal to request that the PCI bus arbiter allow it access to the bus.

PREQ is

updated on the rising edge of PCLK.

Signal Name:

PGNT

Signal Description:

PCI Bus Grant

Signal Type:

Input

The PCI bus arbiter asserts this active-low signal to indicate to the PCI requesting agent that access to the PCI bus

has been granted. The device samples

PGNT on the rising edge of PCLK and, if detected, initiates a bus

transaction when it has sensed that the

PFRAME signal has been deasserted.

Signal Name:

PPERR

Signal Description:

PCI Parity Error

Signal Type:

Input/Output (tri-state capable)

This active-low signal reports parity errors.

PPERR can be enabled and disabled through the PCI configuration

registers. This signal is updated on the rising edge of PCLK.

Signal Name:

PSERR

Signal Description:

PCI System Error

Signal Type:

Output (open drain)

This active-low signal reports any parity errors that occur during the address phase.

PSERR can be enabled and

disabled through the PCI configuration registers. This signal is updated on the rising edge of PCLK.

DS31256 bảng dữ liệu(PDF) 24 Page - Maxim Integrated Products

DS31256 bảng dữ liệu(HTML) 24 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL