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DS31256 bảng dữ liệu(PDF) 80 Page - Maxim Integrated Products |
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DS31256 bảng dữ liệu(HTML) 80 Page - Maxim Integrated Products |
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80 / 183 page ![]() DS31256 256-Channel, High-Throughput HDLC Controller 80 of 183 Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7) 00000000 (00h) = HDLC channel number 1 11111111 (FFh) = HDLC channel number 256 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to write data to the internal transmit starting block pointer RAM, this bit should be written to 1 by the host. This causes the device to take the data that is in the TFSBP register and write it to the channel location indicated by the HCID bits. When the device has completed the write, the IAB is set to 0. Note: The TFSBP register is write-only memory. Once this register has been written to and the operation has started, the DS31256 internal state machine changes the value in this memory. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write operation has completed. Register Name: TFSBP Register Description: Transmit FIFO Starting Block Pointer Register Address: 0984h Bit # 7 6 5 4 3 2 1 0 Name TSBP7 TSBP6 TSBP5 TSBP4 TSBP3 TSBP2 TSBP1 TSBP0 Default Bit # 15 14 13 12 11 10 9 8 Name n/a n/a n/a n/a n/a n/a TSBP9 TSBP8 Default Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 9/Starting Block Pointer (TSBP0 to TSBP9). These bits determine which of the 1024 blocks within the transmit FIFO the host wants the device to configure as the starting block for a particular HDLC channel. Any of the blocks within a chain of blocks for an HDLC channel can be configured as the starting block. When these bits are read, they report the current block pointer being used to read data from the transmit FIFO by the HDLC Layer 2 engines. 0000000000 (000h) = use block 0 as the starting block 0111111111 (1FFh) = use block 511 as the starting block 1111111111 (3FFh) = use block 1023 as the starting block Register Name: TFBPIS Register Description: Transmit FIFO Block Pointer Indirect Select Register Address: 0990h Bit # 7 6 5 4 3 2 1 0 Name BLKID7 BLKID6 BLKID5 BLKID4 BLKID3 BLKID2 BLKID1 BLKID0 Default 0 0 0 0 0 0 0 0 Bit # 15 14 13 12 11 10 9 8 Name IAB IARW n/a n/a n/a n/a BLKID9 BLKID8 Default 0 0 0 0 0 0 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. |
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