DS31256 datasheet(60/183 Pages) MAXIM

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Giải thích chi tiết về linh kiện	256-Channel, High-Throughput HDLC Controller

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DS31256 256-Channel, High-Throughput HDLC Controller

60 of 183

6.5 BERT

The BERT block is capable of generating and detecting the following patterns:

§ The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS

§ A repetitive pattern from 1 to 32 bits in length

§ Alternating (16-bit) words that flip every 1 to 256 words

The BERT receiver has a 32-bit bit counter and a 24-bit error counter. It can generate interrupts upon

detecting a bit error, a change in synchronization, or if an overflow occurs in the bit and error counters.

See Section 5 for details on status bits and interrupts from the BERT block. To activate the BERT block,

the host must configure the BERT mux (Figure 6-7). In channelized applications, the host must also

configure the Layer 1 state machine to send/obtain data to/from the BERT block through the Layer 1

configuration registers (Section 6.3).

Figure 6-7. BERT Mux Diagram

Port 0 (slow)

Port 1 (slow)

Port 2 (slow)

Port 3 (slow)

Port 4 (slow)

Port 5 (slow)

BERT

Mux

BERT

BLOCK

SBERT STATUS

BIT IN SM

INTERNAL CONTROL AND

CONFIGURATION BUS

Port 13 (slow)

Port 14 (slow)

Port 15 (slow)

Port 0 (fast)

Port 1 (fast)

BERT SELECT (5)

IN THE MASTER CONFIGURATION REGISTER

Port 2 (fast)

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