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DS31256 bảng dữ liệu(PDF) 87 Page - Maxim Integrated Products

tên linh kiện DS31256
Giải thích chi tiết về linh kiện  256-Channel, High-Throughput HDLC Controller
PDF  183 Pages
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nhà sản xuất  MAXIM [Maxim Integrated Products]
Trang chủ  https://www.maximintegrated.com/en.html
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DS31256 bảng dữ liệu(HTML) 87 Page - Maxim Integrated Products

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DS31256 256-Channel, High-Throughput HDLC Controller
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Host Actions
The host typically handles the receive DMA as follows:
1) The host is always trying to make free data buffer space available and therefore tries to fill the free-
queue descriptor.
2) The host either polls, or is interrupted, when some incoming packet data is ready for processing.
3) The host then reads the done-queue descriptor circular queue to find out which channel has data
available, what the status is, and where the receive packet descriptor is located.
4) The host then reads the receive packet descriptor and begins processing the data.
5) The host then reads the next descriptor pointer in the link-listed chain and continues this process
until either a number (from 1 to 7) of descriptors have been processed or an end of packet has been
reached.
6) The host then checks the done-queue descriptor circular queue to see if any more data buffers are
ready for processing.



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