DS31256 datasheet(66/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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Bit 1/BERT Error Counter Overflow (BECO). A latched bit that is set when the 24-bit BERT error counter

(BEC) overflows. Cleared when read and is not set again until another overflow occurs.

Bit 2/BERT Bit Counter Overflow (BBCO). A latched bit that is set when the 32-bit BERT bit counter (BBC)

overflows. Cleared when read and is not set again until another overflow occurs.

Bit 3/Bit Error Detected (BED). A latched bit that is set when a bit error is detected. The receive BERT must be

in synchronization for it to detect bit errors. Cleared when read.

Bit 4/Receive Loss of Synchronization (RLOS). A latched bit that is set whenever the receive BERT begins

searching for a pattern. Once synchronization is achieved, this bit remains set until read.

Bit 5/Receive All Zeros (RA0). A latched bit that is set when 31 consecutive 0s are received. Allowed to be

cleared once a 1 is received.

Bit 6/Receive All Ones (RA1). A latched bit that is set when 31 consecutive 1s are received. Allowed to be

cleared once 0 is received.

Bits 8 to 15/BERT 24-Bit Error Counter (BEC). Lower word of the 24-bit error counter. See the BERTEC1

BERTEC1

BERT 24-Bit Error Counter (upper)

051Ch

Bit #

Name

BERT 24-Bit Error Counter

Default

Bit #

Name

BERT 24-Bit Error Counter (upper byte)

Default

Note: Bits that are underlined are read-only; all other bits are read-write. default value for all bits is 0.

Bits 0 to 15/BERT 24-Bit Error Counter (BEC). Upper two words of the 24-bit error counter. This 24-bit

counter increments for each data bit received in error. This counter is not disabled when the receive BERT loses

synchronization. This counter is loaded with the current bit count value when the LC control bit in the BERTC0

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