DS31256 datasheet(25/183 Pages) MAXIM

25 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

25 of 183

Signal Name:

PINTA

Signal Description:

PCI Interrupt

Signal Type:

Output (open drain)

This active-low (open drain) signal is asserted low asynchronously when the device is requesting attention from

the device driver.

PINTA is deasserted when the device-interrupting source has been serviced or masked. This

signal is updated on the rising edge of PCLK.

3.6 PCI Extension Signals

These signals are not part of the normal PCI bus signal set. There are additional signals that are asserted when the

DS31256 is an initiator on the PCI bus to help users interpret the normal PCI bus signal set and connect them to a

non-PCI environment like an Intel i960-type bus.

Signal Name:

PXAS

Signal Description:

PCI Extension Address Strobe

Signal Type:

Output

This active-low signal is asserted low on the same clock edge as

PFRAME and is deasserted after one clock

period. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the

rising edge of PCLK.

Signal Name:

PXDS

Signal Description:

PCI Extension Data Strobe

Signal Type:

Output

This active-low signal is asserted when the PCI bus either contains valid data to be read from the device or can

accept valid data that is written into the device. This signal is only asserted when the device is an initiator. This

signal is an output and is updated on the rising edge of PCLK.

Signal Name:

PXBLAST

Signal Description:

PCI Extension Burst Last

Signal Type:

Output

This active-low signal is asserted on the same clock edge as

PFRAME is deasserted and is deasserted on the same

clock edge as

PIRDY is deasserted. This signal is only asserted when the device is an initiator. This signal is an

output and is updated on the rising edge of PCLK.

3.7 Supply and Test Signal Description

Signal Name:

TEST

Signal Description:

Factory Test Input

Signal Type:

Input (with internal 10kΩ pullup)

This input should be left open-circuited by the user.

Signal Name:

VDD

Signal Description:

Positive Supply

Signal Type:

n/a

3.3V (±10%). All VDD signals should be connected together.

Signal Name:

VSS

Signal Description:

Ground Reference

Signal Type:

n/a

All VSS signals should be connected to the local ground plane.

DS31256 bảng dữ liệu(PDF) 25 Page - Maxim Integrated Products

DS31256 bảng dữ liệu(HTML) 25 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL