DS31256 datasheet(139/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

139 of 183

10.2.2 Status Bits (PCMD0)

The upper word in the PCMD0 register is the status portion, which reports events as they occur. As previously

mentioned, reads of the status portion occur normally but writes are unique in that bits can only be reset (i.e.,

forced to 0). This occurs when 1 is written to a bit position. Writes with a 0 to a bit position have no effect. This

allows individual bits to be reset.

Bits 16 to 20/Reserved. These read-only bits are forced to 0 by the device.

Bit 21/66MHz Capable (66MHz). This read-only bit is forced to 0 by the device to indicate that it is not capable

of running at 66MHz.

Bit 22/User-Definable Features Capable (UDF). This read-only bit is forced to 0 by the device to indicate that it

does not support user-definable features.

Bit 23/Fast Back-to-Back Capable Target (FBBCT). This read-only bit is forced to 1 by the device to indicate

that it is capable of accepting fast back-to-back transactions when the transactions are not from the same agent.

Bit 24/PCI Parity Error Reported (PARR). This read/write bit is set to 1 when the device is a bus master and

detects or asserts the

PPERR signal when the PARC command bit is enabled. This bit can be reset (set to 0) by the

host by writing 1 to this bit.

0 = no parity errors have been detected

1 = parity errors detected

Bits 25, 26/Device Timing Select Bits 0 and 1 (DTS0 and DTS1). These read-only bits are forced to 01b by the

device to indicate that it is capable of the medium timing requirements for the

PDEVSEL signal.

Bit 27/Target Abort Initiated (TABT). This read-only bit is forced to 0 by the device since it does not terminate

a bus transaction with a target abort when the device is a target.

Bit 28/Target Abort Detected by Master (TABTM). This read/write bit is set to 1 when the device is a bus

master and it detects that a bus transaction has been aborted by the target with a target abort. This bit can be reset

(set to 0) by the host by writing 1 to this bit.

Bit 29/Master Abort (MABT). This read/write bit is set to 1 when the device is a bus master and the bus

transaction is terminated with a master abort (except for special cycle). This bit can be reset (set to 0) by the host

by writing 1 to this bit.

Bit 30/PCI System Error Reported (PSE). This read/write bit is set to 1 when the device asserts the

PSERR

signal. This bit can be reset (set to 0) by the host by writing 1 to this bit.

Bit 31/PCI Parity Error Reported (PPE). This read/write bit is set to 1 when the device detects a parity error

(even if parity is disabled through the PARC command bit). This bit can be reset (set to 0) by the host by writing 1

to this bit.

DS31256 bảng dữ liệu(PDF) 139 Page - Maxim Integrated Products