MC68HC908AP16CFB datasheet(108/440 Pages) MOTOROLA

108 / 440 page

Clock Generator Module (CGM)

Data Sheet

MC68HC908AP Family — Rev. 2.5

108

MOTOROLA

The following conditions apply when the PLL is in automatic bandwidth

control mode:

•

The ACQ bit (See 8.5.2 PLL Bandwidth Control Register.) is a

read-only indicator of the mode of the filter. (See 8.3.4

Acquisition and Tracking Modes.)

•

The ACQ bit is set when the VCO frequency is within a certain

tolerance and is cleared when the VCO frequency is out of a

certain tolerance. (See 8.8 Acquisition/Lock Time

Specifications for more information.)

•

The LOCK bit is a read-only indicator of the locked state of the

PLL.

•

The LOCK bit is set when the VCO frequency is within a certain

tolerance and is cleared when the VCO frequency is out of a

certain tolerance. (See 8.8 Acquisition/Lock Time

Specifications for more information.)

•

CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s

lock condition changes, toggling the LOCK bit. (See 8.5.1 PLL

Control Register.)

The PLL also may operate in manual mode (AUTO = 0). Manual mode

is used by systems that do not require an indicator of the lock condition

for proper operation. Such systems typically operate well below

fBUSMAX.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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