CS53L30 datasheet(16/67 Pages) CIRRUS

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DS992F2

CS53L30

3 Characteristics and Specifications

8.Hand-off timing for multidevice

systems (SHIFT_LEFT = 1).

When SHIFT_LEFT = 1, it is

recommended to insert an empty

slot between devices on the

TDM bus to prevent contention

possibilities.

9.In Master Mode, the output sample rate follows the MCLK rate, per Section 4.6.5. MCLK deviations from the nominal supported rates are passed

directly to the output sample rate by the same factor (e.g., a +100 ppm offset in the frequency of MCLK becomes a +100 ppm offset in FSYNC).

10.“n” refers to number of SCLK cycles programmed in LRCK_TPWH[10:3] | LRCK_TPWH[2:0] (see p. 51) when

LRCK_50_NPW (see p. 51) is set;

otherwise, tFSYNC has a 50% duty cycle.

Table 3-13. Switching Specifications—I2C Control Port

Test conditions (unless specified otherwise): Fig. 2-1 shows CS53L30 connections; GNDA = GNDD = 0 V; all voltages are with respect to ground;

Parameters can vary with VA, typical performance data taken with VA = 1.8 V, VP = 3.6 V, min/max performance data taken with VA = 1.8V, VP = 3.6V;

TA = +25°C; logic 0 = ground, logic 1 = VA; input timings are measured at VIL and VIH thresholds, and output timings are measured at VOL and VOH

thresholds (see Table 3-14).

Parameter 1,2

1.All specifications are valid for the signals at the pins of the CS53L30 with the specified load capacitance.

2.I2C control port timing.

Symbol

Min

Max

Unit

RESET rising edge to start

tirs

500

—

SCL clock frequency

fscl

—

550

kHz

Start condition hold time (prior to first clock pulse)

thdst

0.6

—

µs

Clock low time

tlow

1.3

—

µs

Clock high time

thigh

0.6

—

µs

Setup time for repeated start condition

tsust

0.6

—

µs

SDA input hold time from SCL falling 3

3.Data must be held for sufficient time to bridge the transition time, tf, of SCL.

thddi

00.9

µs

SDA output hold time from SCL falling

thddo

0.2

0.9

µs

SDA setup time to SCL rising

tsud

100

—

Rise time of SCL and SDA

trc

—

300

Fall time SCL and SDA

tfc

—

300

Setup time for stop condition

tsusp

0.6

—

µs

Bus free time between transmissions

tbuf

1.3

—

µs

SDA bus capacitance

—

400

SDA pull-up resistance

500

—



SLOTx:LSB+1

SCLK

Device 0: SDOUT

tHOLD2

SLOTx:LSB

SLOTx:MSB

SLOTx:MSB -1

SLOTx:MSB -2

Output Not Driven (Hi-Z)

t buf

t hdst

low

t r

t f

hdd

t high

t sud

tsust

t susp

Stop

Start

Stop

Repeated

SDA

SCL

t irs

RESET

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