CS53L30 datasheet(47/67 Pages) CIRRUS

47 / 67 page

DS992F2

CS53L30

7 Register Descriptions

All registers are read/write except for the chip ID, revision register, and status registers, which are read only. Refer to the

following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or

reset is indicated. All reserved registers must maintain their default state.

7.1 Device ID A and B

Address 0x01

R/O

654

DEVIDA[3:0]

DEVIDB[3:0]

Default

101

7.2 Device ID C and D

Address 0x02

R/O

654

DEVIDC[3:0]

DEVIDD[3:0]

Default

010

7.3 Device ID E

Address 0x03

R/O

654

DEVIDE[3:0]

—

Default

000

Bits

Name

Description

7:4

DEVIDA

DEVIDC

DEVIDE

Device ID code for the CS53L30.

DEVIDA 0x5

DEVIDB 0x3

DEVIDC 0xA Represents the “L” in CS53L30

DEVIDD 0x3

DEVIDE 0x0

3:0

DEVIDB

DEVIDD

7.4 Revision ID

Address 0x05

R/O

654

AREVID[3:0]

MTLREVID[3:0]

Default

xxx

Bits

Name

Description

7:4

AREVID

Alpha revision. CS53L30 alpha revision level. AREVID and MTLREVID form the complete device revision ID (e.g., A0, B2).

0xA A…

0xF F

3:0 MTLREVID Metal revision. CS53L30 metal revision level. AREVID and MTLREVID form the complete device revision ID (e.g., A0, B2).

0x0 0…

0xF F

7.5 Power Control

Address 0x06

R/W

PDN_ULP

PDN_LP

DISCHARGE_FILT+ THMS_PDN

—

Default

Bits

Name

Description

PDN_ULP

CS53L30 power down. Configures the power state of the entire device. After power-up (PDN_ULP: 1

 0), subblocks

stop ignoring their individual power controls and are powered according to their settings. PDN_ULP has precedence over

PDN_LP (i.e., if PDN_ULP is set, the ADC and references are all powered down).

0 (Default) Powered up, as per the individual x_PDN controls.

1 Powered down. After PDN_ULP is set and the entire device is powered down, PDN_DONE is set, indicating that

MCLK can be removed.

PDN_LP

Partial CS53L30 power down. Configures the power state of the device, with the exception of the reference circuits to

allow for faster startup during power cycles. After power up (PDN_LP: 1

0), subblocks stop ignoring their individual

power controls and are powered according to their settings.

0 (Default) Powered up, as per the individual x_PDN controls.

1 Powered down.

Note: If PDN_ULP is set, the value of PDN_LP is ignored.

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