CS53L30 datasheet(55/67 Pages) CIRRUS

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DS992F2

CS53L30

7.29 ADC2/DMIC2 Control 1

Address 0x2D

R/W

ADC2B_PDN ADC2A_PDN

—

DMIC2_PDN DMIC2_SCLK_DIV

—

Default

Bits Name

Description

7,6 ADC2x_

PDN

ADC2x power down. Configures the ADC Channel x power state, including all associated analog front-end circuity (preamp,

PGA, etc.). Enables the channel’s digital decimator associated. Must be cleared if the input channel type is digital.

0 (Default) Powered up

1 Powered down

5:3

—

Reserved

2DMIC2_

PDN

Power down digital mic clock. Determines the power state of the digital mic interface clock

0 Powered up

1 (Default) Powered down

1DMIC2_

SCLK_

DIV

DMIC2 clock divide ratio. Selects the divide ratio between the internal MCLK and the digital mic interface clock output.

Section 4.5 lists supported digital mic interface shift clock rates and their associated programming settings.

0 (Default) 64•Fsint

1 32•Fsint

0—

Reserved

7.30 ADC2/DMIC2 Control 2

Address 0x2E

R/W

432

ADC2_NOTCH_DIS

—

ADC2B_INV ADC2A_INV

—

ADC2B_DIG_BOOST ADC2A_DIG_BOOST

Default

000

Bits

Name

Description

7ADC2_

NOTCH_

DIS

ADC2 digital notch filter disable. Disables the digital notch filter on ADC2.

0 (Default) Enabled

1 Disabled

6—

Reserved

5,4 ADC2x_

INV

ADC2x invert signal polarity. Configures the polarity of the ADC2 Channel x signal.

0 (Default) Not inverted

1Inverted

3:2

—

Reserved

1,0 ADC2x_

DIG_

BOOST

ADC2x digital boost. Configures a +20-dB digital boost on the ADC2 or DMIC signal, based on the input source (see Table 4-5).

0 (Default) No boost applied

1 +20-dB digital boost applied

7.31 ADC2 Control 3

Address 0x2F

R/W

432

—

ADC2_HPF_EN

ADC2_HPF_CF[1:0]

ADC2_NG_ALL

Default

Bits Name

Description

7:4

—

Reserved

3ADC2_

HPF_

ADC2 HPF enable. Configures the internal HPF after ADC2. Change only if the ADC is in a powered down state.

0 Disabled. Clear for test purposes only.

1 (Default) Enabled

2:1 ADC2_

HPF_

ADC2 HPF corner frequency. Sets the corner frequency (–3-dB point) for the internal HPF. Increasing the HPF corner frequency

past the default setting can introduce up to ~0.3 dB of gain in the passband.

00 (Default) 3.88x10–5 x Fsint (1.86 Hz at Fsint = 48 kHz).

01 2.5x10–3xFsint (120 Hz at Fsint = 48 kHz)

10 4.9x10–3xFsint (235 Hz at Fsint = 48 kHz)

11 9.7x10–3xFsint (466 Hz at Fsint = 48 kHz)

0ADC2_

NG_

ALL

ADC2 noise-gate ganging. Configures noise gating for Channels A and B as independent (see ADC1x_NG) or ganged.

0 (Default) Independent noise gating on Channels A and B

1 Ganged noise gating on Channels A and B. Noise gate muting is applied to both channels if the signal amplitude of both

remains below the noise gate AB minimum threshold (see ADC1_NG_THRESH) for longer than the attack delay

(debounce) time (see ADC1_NG_DELAY).

• Noise-gate muting is removed (released) without debouncing when the signal level exceeds the threshold.

• Noise-gate attack and release rates (soft-ramped as a function of Fs or abrupt) are set according to DIGSFT.

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