CS53L30 datasheet(51/67 Pages) CIRRUS

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DS992F2

CS53L30

7.15 LRCK Control 1

Address 0x1B

R/W

654

LRCK_TPWH[10:3]

Default

000

Bits

Name

Description

7:0

LRCK_

TPWH[10:3]

LRCK high-time pulse width [10:3]. With LRCK_TPWH[2:0], sets the number of SCLK cycles for which the LRCK remains

high. Active only when in TDM Mode and LRCK_50_NPW = 1.

0x000 (Default) LRCK high time is 1 SCLK wide

0x001 LRCK high time is 2 SCLKs wide

7.16 LRCK Control 2

Address 0x1C

R/W

7654

—

LRCK_50_NPW

LRCK_TPWH[2:0]

Default

0000

Bits

Name

Description

7:4

—

Reserved

LRCK_50_NPW LRCK either 50% duty cycle or programmable high-time pulse width. In TDM Mode, pulse width can be 50% or

programmable up to 2047 x SCLK cycles.

0 (Default) High-time pulse width set by LRCK_TPWH[10:0].

1 50% duty cycle

2:0 LRCK_TPWH[2:0] LRCK high time pulse width [2:0]. With LRCK_TPWH[10:3], sets the LRCK high time in TDM Mode. See Section 7.15.

7.17 MUTE Pin Control 1

Address 0x1F

R/W

654

3210

MUTE_PDN_

ULP

MUTE_PDN_

—

MUTE_M4B_

PDN

MUTE_M3B_

PDN

MUTE_M2B_

PDN

MUTE_M1B_

PDN

MUTE_MB_

ALL_PDN

Default

000

0000

Bits

Name

Description

MUTE_PDN_ULP

Power down all ADCs, references, and mic biases when the MUTE pin is asserted.

0 (Default) Not affected by MUTE pin

1 Powered down when MUTE pin asserted

MUTE_PDN_LP

Power down all ADCs and mic biases when the MUTE pin is asserted.

0 (Default) Not affected by MUTE pin

1 Powered down when MUTE pin asserted

5—

Reserved

4, 3,

2, 1

MUTE_MxB_PDN

Individual power down controls for the MICx biases when the MUTE pin is asserted.

0 (Default) Not affected by MUTE pin

1 Powered down when MUTE pin asserted

MUTE_MB_ALL_PDN Power down all mic biases when the MUTE pin is asserted.

0 (Default) Not affected by MUTE pin

1 Powered down when MUTE pin asserted

7.18 MUTE Pin Control 2

Address 0x20

R/W

765432

MUTE_PIN_

POLARITY

MUTE_ASP_

TDM_PDN

MUTE_ASP_

SDOUT2_PDN

MUTE_ASP_

SDOUT1_PDN

MUTE_

ADC2B_PDN

MUTE_

ADC2A_PDN

MUTE_

ADC1B_PDN

MUTE_

ADC1A_PDN

Default

10000

000

Bits

Name

Description

MUTE_PIN_

POLARITY

MUTE pin polarity.

0 MUTE pin is active low.

1 (Default) MUTE pin is active high.

MUTE_ASP_TDM_

PDN

Power down TDM when MUTE pin is asserted.

0 (Default) Not affected by MUTE pin.

1 If MUTE_ASP_SDOUT1_PDN is set, the TDM interface is powered down when MUTE pin is asserted.

MUTE_ASP_

SDOUT2_PDN

Power down ASP_SDOUT2 when MUTE pin is asserted. Setting is ignored in TDM Mode.

0 (Default) Not affected by MUTE pin.

1 Powered down when MUTE pin asserted.

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