CS53L30 datasheet(15/67 Pages) CIRRUS

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DS992F2

CS53L30

3 Characteristics and Specifications

Table 3-12. Switching Specifications—Time-Division Multiplexed (TDM) Mode

Test conditions (unless specified otherwise): Fig. 2-1 shows CS53L30 connections; GNDA = GNDD = 0 V; all voltages are with respect to ground;

parameters can vary with VA; typical performance data taken with VA = 1.8 V, VP = 3.6 V; min/max performance data taken with VA = 1.8 V, VP = 3.6 V;

TA = +25°C; Test load for ASP_LRCK/FSYNC, ASP_SCLK, and ASP_SDOUT1 CL = 60 pF; logic 0 = ground, logic 1 = VA; ASPx_DRIVE = 0; input

timings are measured at VIL and VIH thresholds, and output timings are measured at VOL and VOH thresholds (see Table 3-14).

Parameters

Symbol

Min

Max

Units

MCLK frequency

—

1.024

19.2

MHz

MCLK duty cycle

—45

Slave mode

Input sample rate (FSYNC) 1,2

1.Clock rates must be stable when the device is powered up and the serial port is not powered down. Therefore, the appropriate serial port must be

powered down before any clock rates are changed.

2.Maximum frequency for the highest supported nominal rate is indicated.

Table 4-2 shows nominal MCLK rates and their associated configurations.

Fsext

—48

kHz

FSYNC high time pulse 3

3.“n” refers to the total number of SCLKs in one FSYNC frame.

tFSYNC

1/fSCLK

(n–1)/fSCLK

FSYNC setup time before SCLK rising edge

tSETUP1

—

SCLK frequency 4,5

4.If MCLK_19MHZ_EN is set, the maximum SCLK frequency is 6.4 MHz. If SHIFT_LEFT is set, the maximum SCLK frequency is 6.4 MHz.

5.SCLK frequency must be high enough to provide the necessary SCLK cycles to capture all the serial audio port bits.

fSCLK

—12.288

MHz

SCLK duty cycle

—

SDOUT delay time after SCLK rising edge 6

6.Single-device TDM timings

SHIFT_LEFT = 0

tCLK-Q1

—25

SHIFT_LEFT = 1

tCLK-Q1

—45

SDOUT hold time of LSB before transition to Hi-Z

SHIFT_LEFT = 0 [7]

7.Hand-off timing for

multidevice systems

(SHIFT_LEFT = 0.

tHOLD2

SHIFT_LEFT = 1 [8]

tHOLD2

Master mode Output sample rate (FSYNC) 1

Fsext

—

[9]

kHz

FSYNC high time pulse 10

tFSYNC

1/fSCLK

(n–1)/fSCLK

FSYNC setup time before SCLK rising edge

tSETUP1

—

SCLK frequency

fSCLK

(See Table 4-3)MHz

SCLK duty cycle

—

SDOUT delay time after SCLK rising edge

SHIFT_LEFT = 0

tCLK-Q1

—25

SDOUT delay time after SCLK rising edge 6

SHIFT_LEFT = 1

tCLK-Q2

—45

SDOUT hold time of LSB before transition to Hi-Z

SHIFT_LEFT = 0 [7]

tHOLD2

SHIFT_LEFT = 1 [8]

tHOLD2

SLOT0:MSB

FSYNC (programmable

pulse width)

SCLK (SCLK_INV = 0)

SDOUT (SHIFT_LEFT = 0)

tsetup1

tFsync

tCLK-Q1

SLOT0:MSB -1

SLOT0:MSB

SDOUT (SHIFT_LEFT = 1)

tCLK-Q1

SLOT0:MSB -1

SLOT0:MSB -2

SCLK (SCLK_INV = 1)

SLOTx:LSB+1

SCLK

Device 0: SDOUT

tHOLD2

SLOTx:LSB

SLOTx:MSB

Device 1: SDOUT

SLOTx:MSB -1

SLOTx:MSB -2

Output Not Driven (Hi-Z)

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