GD25QL32CXIGX datasheet(29/62 Pages) ELM

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Rev.1.0

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GD25LQ32CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash

7.15. Quad Page Program (32H)

The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2 and IO3.

To use Quad Page Program the Quad enable in status register Bit9 must be set (QE = 1). A Write Enable (WREN)

command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the

Page Program command. The Quad Page Program command is entered by driving CS# Iow, followed by the

command code (32H), three address bytes and at least one data byte on IO pins.

The command sequence is shown in Figure 16. If more than 256 bytes are sent to the device, previously latched

data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page.

If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without

having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last

data byte has been latched in, otherwise the Quad Page Program (PP) command is not executed.

As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated.

While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the

Write In Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program

cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable

Latch (WEL) bit is reset.

A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,

BP1 and BP0) is not executed.

Figure 16. Quad Page Program Sequence Diagram

Command

0 1 2 3 4 5 6 7

32H

CS#

SCLK

8 9 10

28 29 30 31

3 2 1 0

23 22 21

24-bit address

32 33 34 35

4 0

MSB

36 37 38 39

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

Byte1 Byte2

CS#

SCLK

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

42 43 44 45

46 47

50 51 52 53

54 55

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

Byte11

4 0

5 1

6 2

7 3

Byte12

4 0

5 1

6 2

7 3

Byte253

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

Byte256

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