GD25QL32CXIGX datasheet(19/62 Pages) ELM

19 / 62 page

Rev.1.0

62 -

http://www.elm-tech.com

GD25LQ32CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash

Figure 6. Write Status Register Sequence Diagram

Command

0 1 2 3 4 5 6 7

01H

CS#

SCLK

High-Z

8 9 10 11 12 13 14 15

MSB

7 6 5 4 3 2 1 0

Status Register in

16 17 18 19 20 21 22 23

15 14 13 12 11 10 9 8

7.5. Write Status Register (WRSR) (01H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it

can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write En-

able (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register. CS#

must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status

QE bits will be cleared to 0 in SPI mode, while only CMP will be cleared to 0 in QPI mode. As soon as CS# is

driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status

(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when

it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,

BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Ta-

ble1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect

(SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1

and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The

Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered.

Figure 6a. Write Status Register Sequence Diagram (QPI)

CS#

SCLK

IO0

IO1

IO2

IO3

Command

01H

14 10

3 15 11

Status Register in

GD25QL32CXIGX bảng dữ liệu(PDF) 19 Page - ELM Electronics

GD25QL32CXIGX bảng dữ liệu(HTML) 19 Page - ELM Electronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

bảng dữ liệu tải về

Link URL