SPC564A80L7 datasheet(126/157 Pages) STMICROELECTRONICS

tên linh kiện	SPC564A80L7

Giải thích chi tiết về linh kiện	Up to 4 multiply and accumulate operations per cycle

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Electrical characteristics

SPC564A74L7, SPC564A80B4, SPC564A80L7

126/157

Doc ID 15399 Rev 9

3.17.5

External interrupt timing (IRQ pin)

Figure 22.

External Interrupt Timing

3.17.6

eTPU timing

Table 44.

External interrupt timing(1)

Characteristic

Symbol

Min

Max

Unit

IRQ Pulse Width Low

tIPWL

3—

tcyc

IRQ Pulse Width High

tIPWH

3—

tcyc

IRQ Edge to Edge Time(2)

tICYC

6—

tcyc

IRQ timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA =TL to TH.

Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

IRQ

Table 45.

eTPU timing(1)

Characteristic

Symbol

Min

Max

Unit

eTPU Input Channel Pulse Width

tICPW

4—

tcyc

eTPU Output Channel Pulse Width

tOCPW

2(2)

—tcyc

eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA =TL to

TH, and CL = 200 pF with SRC = 0b00.

This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise

and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

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