SPC564A80L7 datasheet(123/157 Pages) STMICROELECTRONICS

123 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Electrical characteristics

Doc ID 15399 Rev 9

123/157

Figure 18.

CLKOUT timing

6tCOV

CLKOUT Posedge to Output Signal Valid

(Output Delay)

ADDR[8:31]

CS[0:3]

DATA[0:31]

RD_WR

WE[0:3]/BE[0:3]

—9

7tCIS

Input Signal Valid to CLKOUT Posedge

(Setup Time)

DATA[0:31]

6.0

—

8tCIH

CLKOUT Posedge to Input Signal Invalid

(Hold Time)

DATA[0:31]

1.0

—

9tAPW

ALE Pulse Width(4)

6.5

—

tAAI

ALE Negated to Address Invalid4

1.5(5)

—ns

External Bus and Calibration bus timing specified at fSYS = 150 MHz and 100 MHz, VDD = 1.14 V to 1.32 V,

VDDE = 3 V to 3.6 V (unless stated otherwise), TA =TL to TH, and CL = 30 pF with DSC = 0b10.

The external bus is limited to half the speed of the internal bus. The maximum external bus frequency is 66 MHz for 16-bit

muxed mode and 33 MHz for non-muxed mode. For The EBI division factor should be set accordingly based on the internal

frequency being used.

Refer to Fast Pad timing in Table 35 and Table 36 (different values for 1.8 V vs. 3.3 V).

Measured at 50% of ALE.

When CAL_TS pad is used for CAL_ALE function the hold time is 1 ns instead of 1.5 ns.

Table 43.

External bus interface (EBI) and calibration bus operation timing (1) (continued)

Symbol

Characteristic

66 MHz (ext. bus)(2)

Unit

Notes

Min

Max

CLKOUT

VDDE/2

Vol_f

Voh_f

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