SPC564A80L7 datasheet(129/157 Pages) STMICROELECTRONICS

tên linh kiện	SPC564A80L7

Giải thích chi tiết về linh kiện	Up to 4 multiply and accumulate operations per cycle

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129 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Electrical characteristics

Doc ID 15399 Rev 9

129/157

Figure 23.

DSPI classic SPI timing — master, CPHA = 0

The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated

based on two SPC564A80 devices communicating over a DSPI link.

The actual minimum SCK cycle time is limited by pad performance.

For DSPI channels using LVDS output operation, up to 40 MHz SCK cycle time is supported. For non-LVDS output,

maximum SCK frequency is 20 MHz. Appropriate clock division must be applied.

The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].

Timing met when pcssck = 3(01), and cssck =2 (0000).

The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].

Timing met when ASC = 2 (0000), and PASC = 3 (01).

10. Timing met when pcssck = 3.

11. Timing met when ASC = 3.

12. This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.

Data

Last Data

First Data

Data

Last Data

SIN

SOUT

PCSx

SCK Output

(CPOL=0)

(CPOL=1)

Note: Refer to Table 48 for the numbers.

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