TNETV2501INPGF datasheet(103/197 Pages) TI1

103 / 197 page

Functional Overview

103

December 2002 − Revised November 2008

SPRS206K

3.11.2.9

Parallel GPIO Data Register 2 (PGPIODAT2)

Reserved

IO45DAT

IO44DAT

IO43DAT

IO42DAT

IO41DAT

IO40DAT

R/W, 00

R/W, pin

IO39DAT

IO38DAT

IO37DAT

IO36DAT

IO35DAT

IO34DAT

IO33DAT

IO32DAT

R/W, pin

LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.

Figure 3−42. Parallel GPIO Data Register 2 Layout (0x4408)

Table 3−44. Parallel GPIO Data Register 2 Bit Field Description†

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15−14

R/W

Reserved

IOxDAT

13−0

R/W

Depends on the signal level on

the corresponding I/O pin

Data bits that are used to either control the level of the

corresponding I/O pins configured as output pins or to

monitor the level of the corresponding I/O pins configured

as input pins. The function of the data register bits is

determined by the setting of the direction register bits. See

Table 3−35, TMS320VC5501 PGPIO Cross-Reference to

determine which device pins correspond to the PGPIO

pins.

If IOxEN = 0 and IOxDIR = 0, then IOxDAT is used to read

the value of the PGPIOx pin:

IOxDAT = 0:

PGPIOx pin is read as a low

IOxDAT = 1:

PGPIOx pin is read as a high

If IOxEN = 1 and IOxDIR = 1, then IOxDAT is used to set

the value of the PGPIOx pin:

IOxDAT = 0:

Set PGPIOx pin to low

IOxDAT = 1:

Set PGPIOx pin to high

Note that other combinations of IOxEN and IOxDIR are

not supported—i.e., IOxEN and IOxDIR must always be

set to the same value.

† x = value from 32 to 45

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