TNETV2501INPGF datasheet(153/197 Pages) TI1

153 / 197 page

Electrical Specifications

153

December 2002 − Revised November 2008

SPRS206K

ECLKOUTx

EMIF.CEx†

EMIF.BE[3:0]

EMIF.A[21:2]

EMIF.D[31:0]

EMIF.ARE/SADS/

SDCAS/SRE§

EMIF.AOE/SOE/SDRAS§

EMIF.AWE/SWE/SDWE§

BE1

BE2

BE3

BE4

PS11

PS3

PS12

PS10

PS4

PS2

PS1

PS8

PS5

PS8

PS10

Write

Latency =

1‡

PS1

PS12

† The write latency and the length of EMIF.CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE

Secondary Control Registers (CEx_SC1, CEx_SC2). In this figure, SYNCWL = 1 and CEEXT = 0.

‡ The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2):

− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

− EMIF.CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, EMIF.CEx goes inactive after the final command has

been issued (CEEXT = 0). For synchronous FIFO interface with glue, EMIF.CEx is active when EMIF.SOE is active (CEEXT = 1).

− Function of EMIF.SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, EMIF.SADS/SRE acts as EMIF.SADS with deselect

cycles (RENEN = 0). For FIFO interface, EMIF.SADS/SRE acts as EMIF.SRE with NO deselect cycles (RENEN = 1).

− Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2

§ EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE operate as EMIF.SADS/SRE, EMIF.SOE, and

EMIF.SWE, respectively, during programmable synchronous interface accesses.

Figure 5−12. Programmable Synchronous Interface Write Timings (With Write Latency = 1)

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