CS5376A datasheet(76/107 Pages) CIRRUS

76 / 107 page

CS5376A

21. BOUNDARY SCAN JTAG

The CS5376A includes an IEEE 1149.1 boundary

scan JTAG port to test PCB interconnections. Refer

to the IEEE 1149.1 specification for more informa-

tion about boundary scan testing.

21.1 Pin Descriptions

TRST - Pin 1

Reset input for the test access port (TAP) controller

and all boundary scan cells, active low. Connect to

GND to disable the JTAG port.

TMS - Pin 2

Serial input to select the JTAG test mode.

TCK - Pin 3

Clock input to the TAP controller.

TDI - Pin 4

Serial input to the scan chain or TAP controller.

TDO - Pin 5

Serial output from the scan chain or TAP control-

ler.

21.2 JTAG Architecture

The JTAG test circuitry consists of a test access

port (TAP) controller and boundary scan cells con-

nected to each pin. The boundary scan cells are

linked together to create a scan chain around the

CS5376A.

21.2.1 JTAG Reset

As required by the IEEE 1149.1 specification, the

JTAG TRST signal is independent of the CS5376A

RESET signal. In systems not using the JTAG port,

TRST should be connected to ground. In systems

using the JTAG port, TRST and RESET should be

independently driven to provide reset capability

during boundry scan.

21.2.2 TAP Controller

The test access port (TAP) controller manages

commands and data through the boundary scan

chain. It supports the four JTAG instructions and

contains the IDCODE listed in Table 18.

The TAP controller also implements the 16 JTAG

state assignments from the IEEE 1149.1 specifica-

tion, which are sequenced using TMS and TCK.

Figure 42. JTAG Block Diagram

TDI

TDO

Controller

TAP

TRST

TMS

TCK

Boundary Scan Cells

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