CS5376A datasheet(62/107 Pages) CIRRUS

62 / 107 page

CS5376A

for one output sample in all channels. The TIME-

BRK digital filter register (0x29) programs the

sample delay for the TB bit output. See “Time

Break Controller” on page 68 for more information

about time break.

FIFO Overflow Bit - W

The FIFO overflow bit indicates an error condition

in the SD port data FIFO, and is set if new digital

filter data overwrites a FIFO location containing

data which has not yet been sent.

The W bit is sticky, meaning it persists indefinitely

once set. Clearing the W bit requires sending the

‘Filter Stop’ and ‘Filter Start’ configuration com-

mands to reinitialize the data FIFO.

Conversion Data Word

The lower 24-bits of the SD port output data word

is the conversion sample for the specified channel.

Conversion data is 24-bit two’s complement for-

mat.

16.3 SD Port Transactions

The SD port can operate in two modes depending

how the SDTKI pin is connected: request mode

where data is output when requested by the com-

munications channel, or continuous mode where

data is output immediately when ready.

16.3.1 Request Mode

To initiate SD port transactions on request, SDTKI

is connected to an active high polling signal from

the communications channel. A rising edge into

SDTKI when new data is available in the SD port

FIFO causes the CS5376A to initiate an SD port

transaction by driving SDRDY low. If data is not

yet available in the SD port FIFO, the SDTKI sig-

nal is passed through to the SDTKO output.

Once an SD port transaction is initiated, serial

clocks into SDCLK cause data to be output to

SDDAT, as shown in Figure 35. When all available

Data

Status

MFLAG

CH[1]

CH[0]

Figure 34. SD Port Data Format

Word 1

Word 4

Word 2

Word 3

Status

Data

128 bits

00 - Channel 1

01 - Channel 2

10 - Channel 3

11 - Channel 4

0 - Modulator Ok

1 - Modulator Error

0 - No Time Break

1 - Time Break

0 - FIFO Ok

1 - FIFO Overflow

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