CS5376A datasheet(61/107 Pages) CIRRUS

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CS5376A

16. SERIAL DATA PORT

Once digital filtering is complete, each 24-bit out-

put sample is combined with an 8-bit status byte.

These 32-bit data words are written to an 8-deep

FIFO buffer and then transmitted to the communi-

cations channel through a high speed serial data

port (SD port).

16.1 Pin Descriptions

SDTKI - Pin 64

Token input, requests an SD port transaction.

SDRDY - Pin 61

Data ready output signal, active low. Open drain

output requiring a 10 k

Ω pull-up resistor.

SDCLK - Pin 62

Serial clock input.

SDDAT - Pin 60

Serial data output. Data valid on rising edge of

SDCLK, transition on falling edge.

SDTKO - Pin 63

Token output, ends an SD port transaction. Passes

through the SDTKI signal when no data is available

in the SD port output FIFO.

16.2 SD Port Data Format

Serial data transactions transfer 32-bit words. Each

word consists of an 8-bit status byte followed by a

24-bit output sample. The status byte, shown in

Figure 34, has an MFLAG bit, channel bits, a time

break bit, and a FIFO overflow bit.

MFLAG Bit - MFLAG

The MFLAG bit is set when an MFLAG signal is

received on the MFLAG1-MFLAG4 pins. When

received, that channel MFLAG bit is set in the next

output word. See “Modulator Interface” on page 39

for more information about MFLAG.

Channel Bits - CH[1:0]

Channel bits indicate from which conversion chan-

nel the data word is from. The channel number,

CH[1:0], is zero based.

CH[1:0] = 00 = Channel 1

CH[1:0] = 01 = Channel 2

CH[1:0] = 10 = Channel 3

CH[1:0] = 11 = Channel 4

Time Break Bit - TB

The time break bit marks a timing reference based

on a rising edge into the TIMEB pin. After a pro-

grammed delay, the TB bit in the status byte is set

CS5376A

SDTKI

SDTKO

Figure 33. Serial Data Port Block Diagram

System Telemetry

SDDAT

SDRDY

SDCLK

Token Out

Token In

Data Ready

Data In

Clock Out

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