TL16PC564BLVI

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS627− SEPTEMBER 2004

12

POST OFFICE BOX 655303

four-and-a-half XIN clock cycles for integer-plus-a-half divisors. Based on the above parameters, the

acceptable XIN/divisor combinations can be derived. The precision of the programmable clock generator for

integer-plus-a-half divisors depends on the closeness to a 50% duty cycle for the XIN input clock.

NOTE

With a divisor less than or equal to 8 (whole number), the UART clock will have a low pulse equal

to one clock cycle of the XIN clock. Caution should be used as noted in the following example.

A 20 MHz clock period yields 50 ns total, including rise time and fall time, if a divisor of less than

or equal to 8 (whole number) is used. This provides a total down period less than 50 ns to the UART

clock, which is less than that which is required for the UART to function properly.

Caution should be used when selecting the XIN and divisor combination.

PGMCLK(0 − 5) VALUE (HEX)

RESULT

0

(0)

No clock (driven high)

0.5

(1)

Divide-by-1

1

(2)

Divide-by-1

1.5

(3)

Divide-by-1

2

(4) to 31.5 (3F)

Divide-by-2 to divide-by-31.5

subsystem serial-bypass mode

The optional serial-bypass mode is implemented to allow a high-throughput path to/from the host CPU. When

this mode is enabled and subsystem control register bit 7 is high, the serial portion of the UART is bypassed

and the subsystem has direct parallel access to the receiver FIFO (write address 140 hex) and the transmitter

FIFO (read address 140 hex). All host CPU interrupts operate normally except for receiver parity, framing, and

breaking interrupts.

auto-CTS operation

The optional auto-CTS operation is implemented so that the host CPU cannot overflow the modem receive

buffer. Auto-CTS operation is enabled when the subsystem sets MCR (subsystem address 130 hex) bit 5 high.

When enabled, deactivating CTS (high) halts the transmitter section of the UART after it completes the current

transfer. Once CTS is reactivated (low) by the modem, transfers resume. Interrupt operation is not affected by

enabling auto-CTS.

auto-RTS operation

The optional auto-RTS operation is implemented so that the subsystem cannot overflow the receiver FIFO.

Auto-RTS operation is enabled when FCR bit 4 is high and EXTEND is low and operates independently from

the trigger-level circuitry. In the 16-byte FIFO mode, the RTS bit in the modem-control register (bit 1) clears when

14 characters are in the receive FIFO. This action causes RTS to go high (inactive). In the 64-byte FIFO mode,

the MCR RTS bit clears when 56 characters are in the receiver FIFO. Interrupt operation is not affected and

operates the same way in either auto-RTS or nonauto-RTS mode. When enabled, a receive-data-

available interrupt occurs after the trigger level is reached. The MCR RTS bit must then be set by the host CPU

after the receiver FIFO has been read.

Not Recommended For New Designs