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TL16PC564BLVIPZ bảng dữ liệu(PDF) 16 Page - Texas Instruments

tên linh kiện TL16PC564BLVIPZ
Giải thích chi tiết về linh kiện  PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
PDF  35 Pages
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nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
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TL16PC564BLVIPZ bảng dữ liệu(HTML) 16 Page - Texas Instruments

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TL16PC564BLVI
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS627− SEPTEMBER 2004
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
host CPU I/O write-cycle timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 3)
MIN
MAX
UNIT
tsu4
Setup time, HD(7 − 0) valid before IOWR
↓
60
ns
th5
Hold time, HA(9 − 0) valid after IOWR
↑
20
ns
tw6
Pulse duration, IOWR low
165
ns
tsu5
Setup time, HA(9 − 0) valid before IOWR
↓
70
ns
th6
Hold time, REG
↑ after IOWR↑
0
ns
tsu6
Setup time, CEx
↓ before IOWR↓
5
ns
th7
Hold time, CEx
↑ after IOWR↑
20
ns
tsu7
Setup time, REG
↓ before IOWR↓
5
ns
th8
Hold time, HD(7 − 0) valid after IOWR
↑
30
ns
transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figure 4)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td9
Delay time, SOUT
↓ after IOWR↑
8
24
Baud
cycles
td10
Delay time, IREQ
↓ after SOUT↓
8
8
Baud
cycles
td11
Delay time, IREQ
↓ after IOWR↑
16
32
Baud
cycles
td12
Delay time, IREQ
↑ after IOWR↑
CL = 100 pF
140
ns
td13
Delay time, IREQ
↑ after IORD↑
CL = 100 pF
140
ns
receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figure 5)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td14
Delay time, sample CLK
↑ after RCLK↑
100
ns
td15
Delay time, IREQ
↓ after SIN↓
1
RCLK
cycles
td16
Delay time, IREQ
↑ after IORD↑
CL = 100 pF
150
ns
modem-control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, CL = 100 pF (see Figure 6)
PARAMETER
MIN
MAX
UNIT
td17
Delay time, RTS, DTR, OUT1, OUT2
↓ or ↑ after IOWR↑
50
ns
td18
Delay time, IREQ
↓ after CTS, DSR, DCD↓
30
ns
td19
Delay time, IREQ
↑ after IORD↑
35
ns
td20
Delay time, IREQ
↓ after RI↑
30
ns
Not Recommended For New Designs



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