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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TL16PC564BLVIPZ bảng dữ liệu(PDF) 18 Page - Texas Instruments |
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TL16PC564BLVIPZ bảng dữ liệu(HTML) 18 Page - Texas Instruments |
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18 / 35 page  TL16PC564BLVI PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER SLLS627− SEPTEMBER 2004 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 subsystem Intel-mode timing requirements (32 MHz) (see Figure 10) INTEL SYMBOL JEDEC SYMBOL MIN MAX UNIT tLHLL tw11 Pulse duration, ALE high 48 ns tAVLL tsu16 Setup time, SA8, SAD(7 − 0) valid to ALE low 21 ns tPLLL td25 Delay time, CS low to ALE low 21 ns tLLAX th15 Hold time, SA8, SAD(7 − 0) valid after ALE ↓ 21 ns tLLWL td26 Delay time, ALE low to WR low 16 ns tLLRL td27 Delay time, ALE low to RD low 16 ns tWHLH td28 Delay time, WR high to ALE high 21 ns tAFRL td29 Delay time, SA8, SAD(7 − 0) in high-impedance state to RD low 0 ns tRLRH tw12 Pulse duration, RD low 120 ns tWLWH tw13 Pulse duration, WR low 120 ns tRHAX td30 Delay time, RD high to SA8, SAD(7 − 0) active 48 ns tWHDX th16 Hold time, SA8, SAD(7 − 0) valid after WR high 48 ns tWHPH td31 Delay time, WR high to CS high 21 ns tRHPH td32 Delay time, RD high to CS high 21 ns tPHPL tw14 Pulse duration, CS high 21 ns subsystem Zilog-mode timing requirements (20 MHz) (see Figure 11) ZILOG SYMBOL JEDEC SYMBOL MIN MAX UNIT tdA(AS) tsu17 Setup time, SA8 and SAD(7 − 0) valid before AS high 20 ns tdAS(A) td33 Delay time, AS high to SA8 and SAD(7 − 0) invalid 35 ns tdAS(DR) td34 Delay time, AS high to data in on SAD(7 − 0) 150 ns twAS tw15 Pulse duration, AS low 35 ns tdA(DS) td35 Delay time, SA8 and SAD(7 − 0) invalid to DS low 0 ns twDS(read) tw16 Pulse duration, DS low (read) 125 ns twDS(write) tw17 Pulse duration, DS low (write) 65 ns tdDS(DR) td36 Delay time, DS low to data in valid 80 ns thDS(DR) th17 Hold time, DS high to data in invalid 0 ns tdDS(A) th18 Hold time, DS high to data out invalid 20 ns tdDS(AS) td37 Delay time, DS high to AS low 30 ns tdDO(DS) td38 Delay time, SAD(7 − 0) (write data from µP) valid to DS low 10 ns tdRW(AS) td39 Delay time, R/W active to AS high 20 ns Not Recommended For New Designs |
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