TL16PC564BLVI

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS627− SEPTEMBER 2004

15

POST OFFICE BOX 655303

XIN timing requirements over recommended operating free-air temperature range (see Figure 1)

TEST CONDITIONS

MIN

MAX

UNIT

Input frequency

VCC = 3.3 V,

See Note 11

50

MHz

Input frequency

VCC = 5 V

60

MHz

tc1

Cycle time, XIN

VCC = 3.3 V,

See Note 11

20

ns

tc1

Cycle time, XIN

VCC = 5 V

16.7

ns

tw1

Pulse duration, XIN clock high

VCC = 3.3 V,

See Note 11

10

ns

tw1

Pulse duration, XIN clock high

VCC = 5 V

8

ns

tw2

Pulse duration, XIN clock low

VCC = 3.3 V,

See Note 11

10

ns

tw2

Pulse duration, XIN clock low

VCC = 5 V

8

ns

NOTE 11: TL16PC564BLVI device tested at VCC = 3 V.

clock switching characteristics over recommended operating free-air temperature range (see

Figure 1)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

td1

Delay time, XIN

↑ to UARTCLK↑

VCC = 3.3 V,

See Note 11

14

ns

td1

Delay time, XIN

↑ to UARTCLK↑

VCC = 5 V

8

ns

td2

Delay time, XIN

↓ to UARTCLK↓

VCC = 3.3 V,

See Note 11

16

ns

td2

Delay time, XIN

↓ to UARTCLK↓

VCC = 5 V

10

ns

td3

Delay time, XIN

↑ to UARTCLK↓

VCC = 3.3 V,

See Note 11

19.8

ns

td3

Delay time, XIN

↑ to UARTCLK↓

VCC = 5 V

13

ns

td4

Delay time, XIN

↑ to UARTCLK↑

VCC = 3.3 V,

See Note 11

20.6

ns

td4

Delay time, XIN

↑ to UARTCLK↑

VCC = 5 V

13.5

ns

td5

Delay time, XIN

↓ to UARTCLK↑

VCC = 3.3 V,

See Note 11

21

ns

td5

Delay time, XIN

↓ to UARTCLK↑

VCC = 5 V

13.8

ns

NOTE 11: TL16PC564BLVI device tested at VCC = 3 V.

host CPU I/O read-cycle timing requirements over recommended ranges of operating free-air

temperature and supply voltage (see Figure 2 and Note 12)

MIN

MAX

UNIT

th1

Hold time, HA(9 − 0) valid after IORD

↑

20

ns

th2

Hold time, REG

↑ valid after IORD↑

0

ns

tw4

Pulse duration, IORD low

165

ns

tsu1

Setup time, HA(9 − 0) valid before IORD

↓

70

ns

tsu2

Setup time, CEx

↓ before IORD↓

5

ns

th3

Hold time, CEx

↑ after IORD↑

20

ns

th4

Hold time, HD(7 − 0) valid after IORD

↑

0

ns

tsu3

Setup time, REG

↓ before IORD↓

5

ns

td6

Delay time, HD(7 − 0) valid after IORD

↓

100

ns

NOTE 12: The maximum load on INPACK is one low power shot with 50-pF total load. All timing is measured in nanoseconds.

host CPU I/O read-cycle switching characteristics over recommended ranges of operating free-air

temperature and supply voltage (see Figure 2 and Note 11)

PARAMETER

MIN

MAX

UNIT

td7

Delay time, INPACK

↓ after IORD↓

45

ns

td8

Delay time, INPACK

↑ after IORD↑

45

ns

NOTE 12: The maximum load on INPACK is one low power Schottky (LSTTL) diode with 50-pF total load. All timing is measured in nanoseconds.

Not Recommended For New Designs