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TL16PC564BLVIPZ bảng dữ liệu(PDF) 17 Page - Texas Instruments

tên linh kiện TL16PC564BLVIPZ
Giải thích chi tiết về linh kiện  PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
PDF  35 Pages
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TL16PC564BLVIPZ bảng dữ liệu(HTML) 17 Page - Texas Instruments

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TL16PC564BLVI
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS627− SEPTEMBER 2004
17
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
host CPU attribute-memory write-cycle timing requirements over recommended ranges of
operating free-air temperature and supply voltage (see Figures 7 and 8)
MIN
MAX
UNIT
tc2
Write cycle tIme, HA(9 − 0)
250
ns
tw8
Pulse duration, WE low
150
ns
tsu8
Setup time, CEx
↓ before WE↑
180
ns
tsu9
Setup time, HA(9 − 0) before WE
↑ (see Note 12)
180
ns
tsu10
Setup time, HA(9 − 0) before WE
↓ and CEx↓(see Note 13)
30
ns
tsu11
Setup time, OE
↑ before WE↓
10
ns
th9
Hold time, HD(7 − 0) after WE
↑
30
ns
trec1
Recovery time, HA(9 − 0) after WE
↑
30
ns
tsu12
Setup time, HD(7 − 0) before WE
↑
80
ns
th10
Hold time, OE
↓ after WE↑
10
ns
tsu13
Setup time, CEx
↓ before WE↓
0
ns
th11
Hold time, CEx
↑ after WE↑
20
ns
NOTE 13: The REG signal timing is identical to address signal timing.
host CPU attribute-memory write-cycle switching characteristics over recommended ranges of
operating free-air temperature and supply voltage (see Figure 7)
PARAMETER
MIN
MAX
UNIT
tdis1
Disable time, HD(7 − 0) after WE
↓
100
ns
tdis2
Disable time, HD(7 − 0) after OE
↑
100
ns
ten1
Enable time, HD(7 − 0) after WE
↑
5
ns
ten2
Enable time, HD(7 − 0) after OE
↓
5
ns
host CPU attribute-memory read-cycle timing requirements over recommended ranges of
operating free-air temperature and supply voltage (see Figure 9)
MIN
MAX
UNIT
tc3
Read cycle time
300
ns
td22
Delay time, HD(7 − 0) after HA(9 − 0)
300
ns
td23
Delay time, HD(7 − 0) after CEx
↓
300
ns
td24
Delay time, HD(7 − 0) after OE
↓
150
ns
th12
Hold time, HD(7 − 0) after HA(9 − 0)
0
ns
tsu14
Setup time, CEx
↓ before OE↓
0
ns
th13
Hold time, HA(9 − 0) after OE
↑
20
ns
tsu15
Setup time, HA(9 − 0) before OE
↓
30
ns
th14
Hold time, CEx
↑ after OE↑
20
ns
host CPU attribute-memory read-cycle switching characteristics over recommended ranges of
operating free-air temperature and supply voltage (see Figure 9)
PARAMETER
MIN
MAX
UNIT
tdis3
Disable time, HD(7 − 0) after CEx
↑
100
ns
tdis4
Disable time, HD(7 − 0) after OE
↑
100
ns
ten3
Enable time, HD(7 − 0) after CEx
↓
5
ns
ten4
Enable time, HD(7 − 0) after OE
↓
5
ns
Not Recommended For New Designs



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