TL16PC564BLVI

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS627− SEPTEMBER 2004

25

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

Data Input Established

HA(9 − 0)

HD(7 − 0) IN

CE1, CE2

tc2

See Note A

OE

WE

tsu8

HD(7 − 0) OUT

tsu9

tsu11

tw8

trec1

th9

tsu12

See Note B

tdis2

ten1

ten2

See Note A

90%

10%

10%

90%

10%

10%

90%

90%

90%

10%

10%

90%

10%

90%

10%

90%

10%

90%

10%

90%

tsu13

th11

tdis1

th10

NOTES: A. The hatched portion may be either high or low.

B. When the data I/O terminal is in the output state, no signals should be applied to HD(7 − 0) by the system.

Figure 7. Host CPU Attribute-Memory Write Timing Waveforms (WE Control)

Not Recommended For New Designs