TL16PC564BLVI

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS627− SEPTEMBER 2004

21

POST OFFICE BOX 655303

host CPU status change timing requirements over recommended ranges of operating free-air

temperature and supply voltage (see Figure 17)

MIN

MAX

UNIT

td54

Delay time, subsystem write

↑ to STSCHG↓ (see Note 14)

2tc5

3tc5

ARBCLKI

cycles

td55

Delay time, OE

↓ to STSCHG high impedance (see Note 15)

tc5

2tc5

ARBCLKI

cycles

NOTES: 15. Synchronized to rising edge of ARBCLKI

16. Synchronized to falling edge of ARBCLKI

PARAMETER MEASUREMENT INFORMATION

XIN

1 XIN Cycle

td1

td2

N

UARTCLK

(1/0.5 − 1/1.5)

UARTCLK†

(1/2 − 1/7)

UARTCLK†

(1/2.5 − 1/7.5)

tc1

tw2

tw1

td3

td4

td5

td3

1.5 XIN Cycles

td4

td3

UARTCLK‡

(1/8 − 1/31)

(N − 1.5)XIN Cycles

(N − 1)XIN Cycles

(N − 4)XIN Cycles

4 XIN Cycles

td5

td3

UARTCLK‡

(1/8.5 − 1/31.5)

(N − 4.5)

XIN Cycles

4.5 XIN Cycles

† The low portion of the UARTCLK cycle = 1 XIN cycle for PGMCLK integer values of 2 to 7 and 1.5 XIN cycles for PGMCLK noninteger values

2.5 to 7.5.

‡ The low portion of the UARTCLK cycle = 4 XIN cycles for PGMCLK integer values of 8 to 31 and 4.5 XIN cycles for PGMCLK noninteger values

8.5 to 31.5.

Figure 1. XIN Clock Timing Waveforms

Not Recommended For New Designs