TL16PC564BLVI

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS627− SEPTEMBER 2004

23

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

REG

IOWR

th5

tsu6

tsu7

tsu5

tw6

th8

tsu4

HA(9 − 0)

CE1, CE2

HD(7 − 0)

th7

th6

50%

50%

10%

10%

10%

10%

50%

50%

NOTE A: All timings are measured at the card. Skews and delays from the system driver/receiver to the card must be accounted for by the system

design.

Figure 3. Host CPU I/O Write Timing Waveforms

Start

Data Bits (5 − 8)

Parity

Stop

Start

SOUT

IREQ

IOWR

(write transmitter

holding register)

IORD

(read interrupt-

identification

register)

td13

td11

50%

50%

50%

50%

50%

50%

50%

50%

td10

td9

td12

Figure 4. Transmitter Timing Waveforms

Not Recommended For New Designs