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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DP83953 bảng dữ liệu(PDF) 7 Page - National Semiconductor (TI) |
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DP83953 bảng dữ liệu(HTML) 7 Page - National Semiconductor (TI) |
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7 / 90 page  2.0 Pin Descriptions (Continued) 7 www.national.com TT = TTL compatible, B = Bi-directional, C = CMOS compatible, OD = Open Drain, I = Input, O = Output, Z = high impedance RTI 67 C O REAL TIME INTERRUPT: A low level on the RTI output indi- cates the RIC2A's real time (packet specific) interrupt logic re- quires CPU attention. The interrupt is cleared by reading the Real Time Interrupt Status register. All interrupt sources may be masked. CDEC 91 TT I COUNTER DECREMENT: A rising edge on the CDEC input strobe decrements all of the RIC2A's Port Event Counters by one. This input is internally synchronized and if necessary the operation of the signal is delayed if there is a simultaneous in- ternally generated counting operation. WR 90 TT I WRITE STROBE: Strobe from the CPU used to write an internal register defined by the RA0 - RA4 inputs. RD 89 TT I READ STROBE: Strobe from the CPU used to read an internal register defined by the RA0 - RA4 inputs. MLOAD 92 TT I DEVICE RESET AND MODE LOAD: When this input cycles back up from low to high, all of the RIC2A's state machines, counters and network ports are reset and held inactive. On the rising edge of MLOAD the logic levels present on the D0 - 7 pins and RA0 - RA4 inputs are latched into the RIC2A's configuration registers. The rising edge of MLOAD also signals the beginning of the display test operation. The clock signal must be present on the CLKIN pin during MLOAD assertion and de-assertion. |
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