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7.0 RIC2A Registers (Continued)

Packet Compress Decode Register (Page 0H Address 18H)

This register is used to determine the number of bytes in the data field of a packet which are transferred over the manage-

ment bus when the packet compress option is employed. The register bits perform the function of a direct binary decode.

Thus up to 255 bytes of data may be transferred over the management bus if packet compression is selected.

Global Security Register (GSR) (Page 0H Address 1DH)

This register provides various security configuration options. For example, enable learning mode for all the ports; starting

address comparison; use the modified packet status register 5 for the management bus; generate random pattern on

source address mismatch; disable port on source address mismatch.

PCD7

PCD6

PCD5

PCD4

PCD3

PCD2

PCD1

PCD0

resv

GLME

resv

DSM

resv

MPS

GRP

SAC

Bit

R/W

Symbol

Description

R/W

SAC

Start Address Comparison

0: Do not begin comparison

1: Begin comparison

R/W

GRP

Generate Random Pattern: This bit controls generating the random pattern on

a valid source address mismatch. In any event, the Hub Manager will be

informed on the SA mismatch.

0: Generate the random pattern

1: Do not generate the random pattern

R/W

MPS

Modify Packet Status Register 5: This bit enables modifying the packet status

0: Do not modify the PSR5

1: Modify the PSR5

resv

Reserved for Future Use

For proper operation, this bit must be 0.

R/W

DSM

Disable the Port on a Source Address Mismatch

0: Do not disable the port on a valid source address mismatch

1: Disable the port on a valid source address mismatch

resv

Reserved for Future Use

R/W

GLME

Global Learn Mode Enable

0: Do not enable the learn mode for all ports

1: Enable the learn mode for all ports

Note: The GLME is not a status bit. Reading this bit indicates what value was

last written to it.

resv

Reserved for Future Use

reads as a logic 0

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