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AM1705DPTP3 bảng dữ liệu(PDF) 48 Page - Texas Instruments |
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AM1705DPTP3 bảng dữ liệu(HTML) 48 Page - Texas Instruments |
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48 / 165 page ![]() AM1705 SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014 www.ti.com 6.6.2 Device Clock Generation PLL0 is controlled by PLL Controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock alignment, and test points. 6.6.3 PLL Controller 0 Registers Table 6-5. PLL Controller 0 Registers BYTE ACRONYM REGISTER DESCRIPTION ADDRESS 0x01C1 1000 REVID Revision Identification Register 0x01C1 10E4 RSTYPE Reset Type Status Register 0x01C1 1100 PLLCTL PLL Control Register 0x01C1 1104 - Reserved 0x01C1 1110 PLLM PLL Multiplier Control Register 0x01C1 1114 PREDIV PLL Pre-Divider Control Register 0x01C1 1118 PLLDIV1 PLL Controller Divider 1 Register 0x01C1 111C PLLDIV2 PLL Controller Divider 2 Register 0x01C1 1120 PLLDIV3 PLL Controller Divider 3 Register 0x01C1 1124 - Reserved 0x01C1 1128 POSTDIV PLL Post-Divider Control Register 0x01C1 1138 PLLCMD PLL Controller Command Register 0x01C1 113C PLLSTAT PLL Controller Status Register 0x01C1 1140 ALNCTL PLL Controller Clock Align Control Register 0x01C1 1144 DCHANGE PLLDIV Ratio Change Status Register 0x01C1 1148 CKEN Clock Enable Control Register 0x01C1 114C CKSTAT Clock Status Register 0x01C1 1150 SYSTAT SYSCLK Status Register 0x01C1 1160 PLLDIV4 PLL Controller Divider 4 Register 0x01C1 1164 PLLDIV5 PLL Controller Divider 5 Register 0x01C1 1168 PLLDIV6 PLL Controller Divider 6 Register 0x01C1 116C PLLDIV7 PLL Controller Divider 7 Register 48 Peripheral Information and Electrical Specifications Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM1705 |
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