AM1705DPTP3 datasheet(16/165 Pages) TI1

16 / 165 page

AM1705

SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014

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3.6.4

External Memory Interface B (SDRAM only)

Table 3-6. External Memory Interface B (EMIFB) Terminal Functions

PIN NO

SIGNAL NAME

TYPE(1)

PULL(2)

MUXED

DESCRIPTION

PTP

EMB_D[15]/GP6[15]

I/O

IPD

EMB_D[14]/GP6[14]

I/O

IPD

EMB_D[13]/GP6[13]

I/O

IPD

EMB_D[12]/GP6[12]

I/O

IPD

EMB_D[11]/GP6[11]

I/O

IPD

EMB_D[10]/GP6[10]

I/O

IPD

EMB_D[9]/GP6[9]

I/O

IPD

EMB_D[8]/GP6[8]

I/O

IPD

GPIO

EMIFB SDRAM data bus

EMB_D[7]/GP6[7]

I/O

IPD

EMB_D[6]/GP6[6]

I/O

IPD

EMB_D[5]/GP6[5]

I/O

IPD

EMB_D[4]/GP6[4]

I/O

IPD

EMB_D[3]/GP6[3]

I/O

IPD

EMB_D[2]/GP6[2]

I/O

IPD

EMB_D[1]/GP6[1]

I/O

IPD

EMB_D[0]/GP6[0]

I/O

IPD

EMB_A[12]/GP3[13]

IPD

EMB_A[11]/GP7[13]

IPD

EMB_A[10]/GP7[12]

105

IPD

EMB_A[9]/GP7[11]

IPD

EMIFB SDRAM row/column

GPIO

address bus

EMB_A[8]/GP7[10]

IPD

EMB_A[7]/GP7[9]

IPD

EMB_A[6]/GP7[8]

IPD

EMB_A[5]/GP7[7]

IPD

EMB_A[4]/GP7[6]

IPD

EMB_A[3]/GP7[5]

100

IPD

EMIFB SDRAM row/column

EMB_A[2]/GP7[4]

101

IPD

address

EMB_A[1]/GP7[3]

102

IPD

GPIO

EMB_A[0]/GP7[2]

103

IPD

EMB_BA[1]/GP7[0]

106

IPU

EMIFB SDRAM bank address

EMB_BA[0]/GP7[1]

107

IPU

EMB_CLK

IPU

EMIF SDRAM clock

EMB_SDCKE

IPU

EMIFB SDRAM clock enable

EMB_WE

IPU

EMIFB write enable

EMIFB SDRAM row address

EMB_RAS

110

IPU

strobe

EMB_CAS

IPU

EMIFB column address strobe

EMB_CS[0]

108

IPU

EMIFB SDRAM chip select 0

EMB_WE_DQM[1] /GP5[14]

IPU

EMIFB write enable/data mask

GPIO

for EMB_D

EMB_WE_DQM[0] /GP5[15]

IPU

(1)

I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (i.e., input versus output), the table reflects the pin function direction for that particular peripheral.

(2)

IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor

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