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UPSD3312D bảng dữ liệu(PDF) 255 Page - STMicroelectronics |
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UPSD3312D bảng dữ liệu(HTML) 255 Page - STMicroelectronics |
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255 / 272 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD33xx DC and AC parameters Doc ID 9685 Rev 7 255/272 Figure 89. Input to output disable / enable tER tEA INPUT INPUT TO OUTPUT ENABLE/DISABLE AI02863 Table 174. CPLD combinatorial timing (5 V PSD module) Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew rate(1) Unit tPD (2) CPLD input pin/feedback to CPLD combinatorial output 20 + 2 + 10 – 2 ns tEA CPLD input to CPLD Output Enable 21 + 10 – 2 ns tER CPLD Input to CPLD Output Disable 21 + 10 – 2 ns tARP CPLD register Clear or Preset delay 21 + 10 – 2 ns tARPW CPLD register Clear or Preset pulse width 10 + 10 ns tARD CPLD array delay Any macrocell 11 + 2 ns 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only) Table 175. CPLD combinatorial timing (3 V PSD module) Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew rate (1) Unit tPD (2) CPLD input pin/feedback to CPLD combinatorial output 35 + 4 + 15 – 6 ns tEA CPLD input to CPLD Output Enable 38 +15 – 6 ns tER CPLD input to CPLD Output Disable 38 + 15 – 6 ns tARP CPLD register Clear or Preset delay 35 + 15 – 6 ns tARPW CPLD register Clear or Preset pulse width 18 + 15 ns tARD CPLD Array Delay Any macrocell 20 + 4 ns 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only) |
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