UPSD3312D datasheet(78/272 Pages) STMICROELECTRONICS

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I/O ports of MCU module

UPSD33xx

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Doc ID 9685 Rev 7

Reading port pin vs. reading port latch

When firmware reads the GPIO ports, sometimes the actual port pin is sampled in

hardware, and sometimes the port SFR latch is read and not the actual pin, depending on

the type of MCU instruction used. These two data paths are shown in Figure 16 through

Figure 18 on page 80. SFR latches are read (and not the pins) only when the read is part of

a read-modify-write instruction and the write destination is a bit or bits in a port SFR. These

instructions are: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ, MOV, CLR, and SETB. All

other types of reads to port SFRs will read the actual pin logic level and not the port latch.

This is consistent with 8051 architecture.

Figure 15.

MCU module port pin function routing

GPIO (8)

UART0 (2)

TIMER0/1 (4)

C (2)

GPIO (8)

TIMER2 (2)

UART1 (2)

SPI (4)

ADC (8)

PCA (8)

8032 MCU

CORE

Low Addr & Data[7:0]

Hi Address [11:8]

Hi Address [15:12]

Available on PSD

Module Pins

MCU Module

On 80-pin

Devices

Only

Ports

RD, WR, PSEN, ALE

SFR

AI09199

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