UPSD3312D datasheet(86/272 Pages) STMICROELECTRONICS

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MCU bus interface

UPSD33xx

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Doc ID 9685 Rev 7

Note:

A PSEN bus cycle in progress may be aborted before completion if the PFQ and Branch

Cache (BC) determines the current code fetch cycle is not needed.

Whenever the same number of MCU_CLK periods is specified in BUSCON for both PSEN

and RD cycles, the bus cycle timing is typically identical for each of these types of bus

cycles. In this case, the only time PSEN read cycles are longer than RD read cycles is when

the PFQ issues a stall while reloading. PFQ stalls do not affect RD read cycles. By

comparison, in many traditional 8051 architectures, RD bus cycles are always longer than

PSEN bus cycles.

18.2

Bus write cycles (WR)

When the WR signal is used, a byte of data is written directly to the PSD module or external

device, no PFQ or caching is involved. Bits in the BUSCON register determine the number

of MCU_CLK periods for bus write cycles to all addresses. It is not possible to specify in

BUSCON a different number of MCU_CLK periods for writes to various address ranges.

18.3

Controlling the PFQ and BC

The BUSCON register allows firmware to enable and disable the PFQ and BC at run-time.

Sometimes it may be desired to disable the PFQ and BC to ensure deterministic execution.

The dynamic action of the PFQ and BC may cause varying program execution times

depending on the events that happen prior to a particular section of code of interest. For this

reason, it is not recommended to implement timing loops in firmware, but instead use one of

the many hardware timers in the UPSD33xx.

By default, the PFQ and BC are enabled after a reset condition.

Note:

Important: Disabling the PFQ or BC will seriously reduce MCU performance.

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