UPSD3312D datasheet(39/272 Pages) STMICROELECTRONICS

tên linh kiện	UPSD3312D

Giải thích chi tiết về linh kiện	fast 8032 MCU with programmable logic

PDF	272 Pages

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nhà sản xuất	STMICROELECTRONICS [STMicroelectronics]

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UPSD33xx

8032 MCU registers

Doc ID 9685 Rev 7

39/272

7.7.5

Overflow flag (OV)

The OV flag is set when: an ADD, ADDC, or SUBB instruction causes a sign change; a MUL

instruction results in an overflow (result greater than 255); a DIV instruction causes a divide-

by-zero condition. The OV flag is cleared by the ADD, ADDC, SUBB, MUL, and DIV

instructions in all other cases. The CLRV instruction will clear the OV flag at any time.

7.7.6

Parity flag (P)

The P flag is set if the sum of the eight bits in the Accumulator is odd, and P is cleared if the

sum is even.

Table 4.

Figure 11.

Program Status Word (PSW) register

RS1

RS0

8032 internal DATA address

00h - 07h

08h - 0Fh

10h - 17h

18h - 1Fh

AI06639

Reset Value 00h

Parity Flag

Bit not assigned

Overflow Flag

(to select Bank0-3)

Carry Flag

Auxillary Carry Flag

General Purpose Flag

AC FO RS1 RS0 OV

MSB

LSB

PSW

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