UPSD3312D datasheet(71/272 Pages) STMICROELECTRONICS

71 / 272 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD33xx

Power saving modes

Doc ID 9685 Rev 7

71/272

15.2

Power-down mode

Power-down mode will halt the 8032 core and all MCU peripherals (Power-down mode

blocks MCU_CLK and PERIPH_CLK). This is the lowest power state for the MCU module.

When the PSD module is also placed in Power-down mode, the lowest total current

consumption for the combined die is achieved for the UPSD33xx. See Section 27.1.16:

Power management on page 170 in the PSD module section for details on how to also place

the PSD module in Power-down mode. The sequence of 8032 instructions is important

when placing both modules into Power-down mode.

The instruction that sets the PD Bit in the SFR named PCON (Table 31 on page 72) is the

last instruction executed prior to the MCU module going into Power-down mode. Once in

Power-down mode, the on-chip oscillator circuitry and all clocks are stopped. The SFRs,

DATA, IDATA, and XDATA are preserved.

Power-down mode is terminated only by a reset from the supervisor, originating from the

RESET_IN_ pin, the low-Voltage Detect circuit (LVD), or a JTAG debug reset command.

Since the clock to the WTD is not active during Power-down mode, it is not possible for the

supervisor to generate a WDT reset.

Table 29 on page 72 summarizes the status of I/O pins and peripherals during Idle and

Power-down modes on the MCU module. Table 30 on page 72 shows the state of 8032

MCU address, data, and control signals during these modes.

15.3

Reduced frequency mode

The 8032 MCU consumes less current when operating at a lower clock frequency. The MCU

can reduce it’s own clock frequency at run-time by writing to three bits, CPUPS[2:0], in the

SFR named CCON0 described in Table 27 on page 69. These bits effectively divide the

clock frequency (fOSC) coming in from the external crystal or oscillator device. The clock

division range is from 1/2 to 1/2048, and the resulting frequency is fMCU.

This MCU clock division does not affect any of the peripherals, except for the WTD. The

clock driving the WTD is the same clock driving the 8032 MCU core as shown in Figure 13

on page 69.

MCU firmware may reduce the MCU clock frequency at run-time to consume less current

when performing tasks that are not time critical, and then restore full clock frequency as

required to perform urgent tasks.

Returning to full clock frequency is done automatically upon an MCU interrupt, if the CPUAR

Bit in the SFR named CCON0 is set (the interrupt will force CPUPS[2:0] = 000). This is an

excellent way to conserve power using a low frequency clock until an event occurs that

requires full performance. See Table 27 on page 69 for details on CPUAR.

See the DC Specifications at the end of this document to estimate current consumption

based on the MCU clock frequency.

Note:

Some of the bits in the PCON SFR shown in Table 31 on page 72 are not related to power

control.

UPSD3312D bảng dữ liệu(PDF) 71 Page - STMicroelectronics

UPSD3312D bảng dữ liệu(HTML) 71 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL