UPSD3312D datasheet(220/272 Pages) STMICROELECTRONICS

220 / 272 page

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PSD module

UPSD33xx

220/272

Doc ID 9685 Rev 7

Figure 74.

Port B structure

Port pins PB0-PB3 are capable of Fast Slew Rate output drive option. Port pins PB4-PB7 are capable of Open Drain output

option.

27.4.49

Port C structure

Port C supports the following operating modes on pins PC2, PC3, PC4, PC7:

●

MCU I/O mode

●

GPLD Output mode from Output Macrocells MCELLBC2, MCELLBC3, MCELLBC4,

MCELLBC7

●

GPLD Input mode to Input Macrocells IMCC2, IMCC3, IMCC4, IMCC7

See Figure 75 on page 222 for detail.

Port C pins can also be configured in PSDsoft for other dedicated functions:

●

Pins PC3 and PC4 support TSTAT and TERR status indicators, to reduce the amount

of time required for JTAG ISP programming. These two pins must be used together for

this function, adding to the four standard JTAG signals. When TSTAT and TERR are

I/O PORT B

LOGIC

DIRECTION

DRIVE SELECT

CONTROL

DATA OUT

(MCUI/O)

ENABLE OUT

DATA IN (MCUI/O)

PT OUTPUT ENABLE (.OE)

LATCHED ADDR BIT

OUTPUT

ENABLE

OUTPUT

ENABLE

TYPICAL

PIN, PORT B

PSD MODULE RESET

ONE of 6

CSIOP

REGISTERS

OUTPUT

SELECT

FROM OMC OUTPUT

(MCELLABx or MCELLBCx)

FROM PLD

INPUT BUS

FROM AND-

OR ARRAY

FROM OMC

ALLOCATOR

CLR

DIRECTION

DRIVE

CONTROL

(MCUI/O)

DATA OUT

8032

RESET

PSDsoft

8032 RD

TO IMCs

CSIOP

REGIS-

TERS

DRIVE TYPE SELECT

(1)

8032

DATA

BITS

8032

DATA

BIT

PIN INPUT

CMOS

BUFFER

HYSTERESIS

VDD

OUTPUT

1 = OPEN

DRAIN,

PB4 - PB7

1 = FAST

SLEW RATE,

PB0 - PB3

IMCB0 - IMCB7

AI09180

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